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target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs
Added oslar_write function to OSLAR_EL1 sysreg, using a status variable in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked to the newly added read-only OSLSR_EL1 register. Linux reads from this register during its suspend/resume procedure. Backports commit 1424ca8d4320427c3e93722b65e19077969808a2 from qemu
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@ -382,6 +382,7 @@ typedef struct CPUARMState {
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uint64_t dbgwvr[16]; /* watchpoint value registers */
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uint64_t dbgwcr[16]; /* watchpoint control registers */
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uint64_t mdscr_el1;
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uint64_t oslsr_el1; /* OS Lock Status */
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/* If the counter is enabled, this stores the last time the counter
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* was reset. Otherwise it stores the counter value
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*/
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@ -3089,6 +3089,23 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
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return CP_ACCESS_OK;
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}
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static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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/* Writes to OSLAR_EL1 may update the OS lock status, which can be
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* read via a bit in OSLSR_EL1.
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*/
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int oslock;
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if (ri->state == ARM_CP_STATE_AA32) {
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oslock = (value == 0xC5ACCE55);
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} else {
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oslock = value & 1;
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}
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env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
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}
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static const ARMCPRegInfo debug_cp_reginfo[] = {
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/* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
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* debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
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@ -3111,9 +3128,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
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{ "MDCCSR_EL0", 14,0,1, 2,0,0, ARM_CP_STATE_BOTH,
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ARM_CP_ALIAS, PL1_R, 0, NULL, 0, offsetof(CPUARMState, cp15.mdscr_el1), {0, 0},
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NULL, NULL, NULL, NULL, NULL, NULL },
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/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
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{ "OSLAR_EL1", 14,1,0, 2,0,4, ARM_CP_STATE_BOTH,
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ARM_CP_NOP, PL1_W, },
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{ "OSLAR_EL1", 14,1,0, 2,0,4, ARM_CP_STATE_BOTH, ARM_CP_NO_RAW,
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PL1_W, 0, NULL, 0, 0, {0, 0},
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NULL, NULL, oslar_write },
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{ "OSLSR_EL1", 14,1,1, 2,0,4, ARM_CP_STATE_BOTH, 0,
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PL1_R, 0, NULL, 10, offsetof(CPUARMState, cp15.oslsr_el1) },
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/* Dummy OSDLR_EL1: 32-bit Linux will read this */
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{ "OSDLR_EL1", 14,1,3, 2,0,4, ARM_CP_STATE_BOTH,
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ARM_CP_NOP, PL1_RW, },
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