yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-22 12:41:01 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #259 from lunixbochs/multiarch

Browse source 
improve multiarch support
This commit is contained in:
Nguyen Anh Quynh 2015-11-12 15:11:06 +08:00
parent d92d6791b9 ad5cd37551
commit d126644bb2
7 changed files with 64 additions and 64 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
qemu/tcg/aarch64/tcg-target.c
View file

@ -1718,10 +1718,10 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
static void tcg_target_init(TCGContext *s) static void tcg_target_init(TCGContext *s)
{ {
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0, tcg_regset_set32(s->tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_X0) | (1 << TCG_REG_X1) | (1 << TCG_REG_X0) | (1 << TCG_REG_X1) |
(1 << TCG_REG_X2) | (1 << TCG_REG_X3) | (1 << TCG_REG_X2) | (1 << TCG_REG_X3) |
(1 << TCG_REG_X4) | (1 << TCG_REG_X5) | (1 << TCG_REG_X4) | (1 << TCG_REG_X5) |
@ -1739,7 +1739,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
tcg_add_target_add_op_defs(aarch64_op_defs); tcg_add_target_add_op_defs(s, aarch64_op_defs);
} }
/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */ /* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */

6
qemu/tcg/arm/tcg-target.c
View file

@ -1994,8 +1994,8 @@ static void tcg_target_init(TCGContext *s)
} }
} }
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0, tcg_regset_set32(s->tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_R0) | (1 << TCG_REG_R0) |
(1 << TCG_REG_R1) | (1 << TCG_REG_R1) |
(1 << TCG_REG_R2) | (1 << TCG_REG_R2) |
@ -2008,7 +2008,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC);
tcg_add_target_add_op_defs(arm_op_defs); tcg_add_target_add_op_defs(s, arm_op_defs);
} }
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,

68
qemu/tcg/ia64/tcg-target.c
View file

@ -2386,42 +2386,42 @@ static void tcg_target_qemu_prologue(TCGContext *s)
static void tcg_target_init(TCGContext *s) static void tcg_target_init(TCGContext *s)
{ {
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], tcg_regset_set(s->tcg_target_available_regs[TCG_TYPE_I32],
0xffffffffffffffffull); 0xffffffffffffffffull);
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], tcg_regset_set(s->tcg_target_available_regs[TCG_TYPE_I64],
0xffffffffffffffffull); 0xffffffffffffffffull);
tcg_regset_clear(tcg_target_call_clobber_regs); tcg_regset_clear(s->tcg_target_call_clobber_regs);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R8);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R9);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R10);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R11);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R14);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R15);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R16);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R17);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R18);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R19);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R20);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R21);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R22);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R23);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R24);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R25);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R26);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R27);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R28);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R29);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R30);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R31);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R56);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R57);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R58);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R59);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R60);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R61);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R62);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R63);
tcg_regset_clear(s->reserved_regs); tcg_regset_clear(s->reserved_regs);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* zero register */
@ -2442,5 +2442,5 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6); tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7); tcg_regset_set_reg(s->reserved_regs, TCG_REG_R7);
tcg_add_target_add_op_defs(ia64_op_defs); tcg_add_target_add_op_defs(s, ia64_op_defs);
} }

6
qemu/tcg/mips/tcg-target.c
View file

@ -1776,8 +1776,8 @@ static void tcg_target_qemu_prologue(TCGContext *s)
static void tcg_target_init(TCGContext *s) static void tcg_target_init(TCGContext *s)
{ {
tcg_target_detect_isa(); tcg_target_detect_isa();
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff); tcg_regset_set(s->tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);
tcg_regset_set(tcg_target_call_clobber_regs, tcg_regset_set(s->tcg_target_call_clobber_regs,
(1 << TCG_REG_V0) | (1 << TCG_REG_V0) |
(1 << TCG_REG_V1) | (1 << TCG_REG_V1) |
(1 << TCG_REG_A0) | (1 << TCG_REG_A0) |
@ -1805,7 +1805,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
tcg_add_target_add_op_defs(mips_op_defs); tcg_add_target_add_op_defs(s, mips_op_defs);
} }
void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)

8
qemu/tcg/ppc/tcg-target.c
View file

@ -2534,9 +2534,9 @@ static void tcg_target_init(TCGContext *s)
have_isa_2_06 = true; have_isa_2_06 = true;
} }
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0, tcg_regset_set32(s->tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_R0) | (1 << TCG_REG_R0) |
(1 << TCG_REG_R2) | (1 << TCG_REG_R2) |
(1 << TCG_REG_R3) | (1 << TCG_REG_R3) |
@ -2564,7 +2564,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
} }
tcg_add_target_add_op_defs(ppc_op_defs); tcg_add_target_add_op_defs(s, ppc_op_defs);
} }
#ifdef __ELF__ #ifdef __ELF__

24
qemu/tcg/s390/tcg-target.c
View file

@ -2283,21 +2283,21 @@ static void tcg_target_init(TCGContext *s)
{ {
query_facilities(); query_facilities();
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
tcg_regset_clear(tcg_target_call_clobber_regs); tcg_regset_clear(s->tcg_target_call_clobber_regs);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R0);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R1); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R1);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R2);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R3);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R4);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R5);
/* The r6 register is technically call-saved, but it's also a parameter /* The r6 register is technically call-saved, but it's also a parameter
register, so it can get killed by setup for the qemu_st helper. */ register, so it can get killed by setup for the qemu_st helper. */
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R6);
/* The return register can be considered call-clobbered. */ /* The return register can be considered call-clobbered. */
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); tcg_regset_set_reg(s->tcg_target_call_clobber_regs, TCG_REG_R14);
tcg_regset_clear(s->reserved_regs); tcg_regset_clear(s->reserved_regs);
tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); tcg_regset_set_reg(s->reserved_regs, TCG_TMP0);
@ -2305,7 +2305,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
tcg_add_target_add_op_defs(s390_op_defs); tcg_add_target_add_op_defs(s, s390_op_defs);
} }
#define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \

8
qemu/tcg/sparc/tcg-target.c
View file

@ -1560,10 +1560,10 @@ static void tcg_target_init(TCGContext *s)
} }
#endif #endif
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64); tcg_regset_set32(s->tcg_target_available_regs[TCG_TYPE_I64], 0, ALL_64);
tcg_regset_set32(tcg_target_call_clobber_regs, 0, tcg_regset_set32(s->tcg_target_call_clobber_regs, 0,
(1 << TCG_REG_G1) | (1 << TCG_REG_G1) |
(1 << TCG_REG_G2) | (1 << TCG_REG_G2) |
(1 << TCG_REG_G3) | (1 << TCG_REG_G3) |
@ -1589,7 +1589,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T1); /* for internal use */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_T2); /* for internal use */
tcg_add_target_add_op_defs(sparc_op_defs); tcg_add_target_add_op_defs(s, sparc_op_defs);
} }
#if SPARC64 #if SPARC64