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target-mips: add SIGRIE instruction

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Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and
microMIPS.
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.

Backports commit bb238210bb096534b68dab15a87c6ff0bef43672 from qemu
This commit is contained in:
Yongbok Kim 2018-02-17 14:45:00 -05:00 committed by Lioncash
parent 4544aa4134
commit d4213b6389
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 11 additions and 1 deletions
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12
qemu/target-mips/translate.c
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@ -320,6 +320,7 @@ enum {
OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM,
OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
@ -12139,7 +12140,8 @@ enum {
LSA = 0x0f,
ALIGN = 0x1f,
EXT = 0x2c,
POOL32AXF = 0x3c
POOL32AXF = 0x3c,
SIGRIE = 0x3f
};
/* POOL32AXF encoding of minor opcode field extension */
@ -13764,6 +13766,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case BREAK32:
generate_exception_end(ctx, EXCP_BREAK);
break;
case SIGRIE:
check_insn(ctx, ISA_MIPS32R6);
generate_exception_end(ctx, EXCP_RI);
break;
default:
pool32a_invalid:
MIPS_INVAL("pool32a");
@ -19138,6 +19144,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SIGRIE:
check_insn(ctx, ISA_MIPS32R6);
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
/* Break the TB to be able to sync copied instructions