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target/arm: Cache the GP bit for a page in MemTxAttrs

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Caching the bit means that we will not have to re-walk the
page tables to look up the bit during translation.

Backports commit 1bafc2ba7e6bfe89fff3503fdac8db39c973de48 from qemu
This commit is contained in:
Richard Henderson 2019-02-05 17:02:17 -05:00 committed by Lioncash
parent 9c2a5963d0
commit d594b2047f
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 0 deletions
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6
qemu/target/arm/helper.c
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@ -9679,6 +9679,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
bool ttbr1_valid; bool ttbr1_valid;
uint64_t descaddrmask; uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el); bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
/* TODO: /* TODO:
* This code does not handle the different format TCR for VTCR_EL2. * This code does not handle the different format TCR for VTCR_EL2.
@ -9859,6 +9860,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
} }
/* Merge in attributes from table descriptors */ /* Merge in attributes from table descriptors */
attrs |= nstable << 3; /* NS */ attrs |= nstable << 3; /* NS */
guarded = extract64(descriptor, 50, 1); /* GP */
if (param.hpd) { if (param.hpd) {
/* HPD disables all the table attributes except NSTable. */ /* HPD disables all the table attributes except NSTable. */
break; break;
@ -9904,6 +9906,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
*/ */
txattrs->secure = false; txattrs->secure = false;
} }
/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
txattrs->target_tlb_bit0 = true;
}
if (cacheattrs != NULL) { if (cacheattrs != NULL) {
if (mmu_idx == ARMMMUIdx_S2NS) { if (mmu_idx == ARMMMUIdx_S2NS) {