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target-arm: Add the Hypervisor timer

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Backports commit b0e66d95e4f587b5818d2760668301ee0871ba5e from qemu
This commit is contained in:
Lioncash 2018-02-14 20:14:33 -05:00
parent ba27ba76a4
commit d706680ad6
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GPG key ID: 4E3C3CC1031BA9C7
18 changed files with 74 additions and 1 deletions
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1
qemu/aarch64.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_aarch64
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64
#define arm_gt_htimer_cb arm_gt_htimer_cb_aarch64
#define arm_handle_psci_call arm_handle_psci_call_aarch64
#define arm_is_psci_call arm_is_psci_call_aarch64
#define arm_is_secure arm_is_secure_aarch64

1
qemu/aarch64eb.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_aarch64eb
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64eb
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64eb
#define arm_gt_htimer_cb arm_gt_htimer_cb_aarch64eb
#define arm_handle_psci_call arm_handle_psci_call_aarch64eb
#define arm_is_psci_call arm_is_psci_call_aarch64eb
#define arm_is_secure arm_is_secure_aarch64eb

1
qemu/arm.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_arm
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_arm
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_arm
#define arm_gt_htimer_cb arm_gt_htimer_cb_arm
#define arm_handle_psci_call arm_handle_psci_call_arm
#define arm_is_psci_call arm_is_psci_call_arm
#define arm_is_secure arm_is_secure_arm

1
qemu/armeb.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_armeb
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_armeb
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_armeb
#define arm_gt_htimer_cb arm_gt_htimer_cb_armeb
#define arm_handle_psci_call arm_handle_psci_call_armeb
#define arm_is_psci_call arm_is_psci_call_armeb
#define arm_is_secure arm_is_secure_armeb

1
qemu/header_gen.py
View file

@ -156,6 +156,7 @@ symbols = (
'arm_gen_test_cc',
'arm_gt_ptimer_cb',
'arm_gt_vtimer_cb',
'arm_gt_htimer_cb',
'arm_handle_psci_call',
'arm_is_psci_call',
'arm_is_secure',

1
qemu/m68k.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_m68k
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_m68k
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_m68k
#define arm_gt_htimer_cb arm_gt_htimer_cb_m68k
#define arm_handle_psci_call arm_handle_psci_call_m68k
#define arm_is_psci_call arm_is_psci_call_m68k
#define arm_is_secure arm_is_secure_m68k

1
qemu/mips.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_mips
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips
#define arm_gt_htimer_cb arm_gt_htimer_cb_mips
#define arm_handle_psci_call arm_handle_psci_call_mips
#define arm_is_psci_call arm_is_psci_call_mips
#define arm_is_secure arm_is_secure_mips

1
qemu/mips64.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_mips64
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64
#define arm_gt_htimer_cb arm_gt_htimer_cb_mips64
#define arm_handle_psci_call arm_handle_psci_call_mips64
#define arm_is_psci_call arm_is_psci_call_mips64
#define arm_is_secure arm_is_secure_mips64

1
qemu/mips64el.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_mips64el
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64el
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64el
#define arm_gt_htimer_cb arm_gt_htimer_cb_mips64el
#define arm_handle_psci_call arm_handle_psci_call_mips64el
#define arm_is_psci_call arm_is_psci_call_mips64el
#define arm_is_secure arm_is_secure_mips64el

1
qemu/mipsel.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_mipsel
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_mipsel
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_mipsel
#define arm_gt_htimer_cb arm_gt_htimer_cb_mipsel
#define arm_handle_psci_call arm_handle_psci_call_mipsel
#define arm_is_psci_call arm_is_psci_call_mipsel
#define arm_is_secure arm_is_secure_mipsel

1
qemu/powerpc.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_powerpc
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_powerpc
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_powerpc
#define arm_gt_htimer_cb arm_gt_htimer_cb_powerpc
#define arm_handle_psci_call arm_handle_psci_call_powerpc
#define arm_is_psci_call arm_is_psci_call_powerpc
#define arm_is_secure arm_is_secure_powerpc

1
qemu/sparc.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_sparc
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc
#define arm_gt_htimer_cb arm_gt_htimer_cb_sparc
#define arm_handle_psci_call arm_handle_psci_call_sparc
#define arm_is_psci_call arm_is_psci_call_sparc
#define arm_is_secure arm_is_secure_sparc

1
qemu/sparc64.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_sparc64
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc64
#define arm_gt_htimer_cb arm_gt_htimer_cb_sparc64
#define arm_handle_psci_call arm_handle_psci_call_sparc64
#define arm_is_psci_call arm_is_psci_call_sparc64
#define arm_is_secure arm_is_secure_sparc64

1
qemu/target-arm/cpu-qom.h
View file

@ -220,6 +220,7 @@ int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
/* Callback functions for the generic timer's timers. */
void arm_gt_ptimer_cb(void *opaque);
void arm_gt_vtimer_cb(void *opaque);
void arm_gt_htimer_cb(void *opaque);
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);

2
qemu/target-arm/cpu.c
View file

@ -355,6 +355,8 @@ static void arm_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
arm_gt_ptimer_cb, cpu);
cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_vtimer_cb, cpu);
cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_htimer_cb, cpu);
//qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
// ARRAY_SIZE(cpu->gt_timer_outputs));
#endif

3
qemu/target-arm/cpu.h
View file

@ -117,7 +117,8 @@ typedef struct ARMGenericTimer {
#define GTIMER_PHYS 0
#define GTIMER_VIRT 1
#define NUM_GTIMERS 2
#define GTIMER_HYP 2
#define NUM_GTIMERS 3
typedef struct {
uint64_t raw_tcr;

55
qemu/target-arm/helper.c
View file

@ -1236,6 +1236,34 @@ static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
gt_recalc_timer(cpu, GTIMER_VIRT);
}
static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
gt_timer_reset(env, ri, GTIMER_HYP);
}
static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_cval_write(env, ri, GTIMER_HYP, value);
}
static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return gt_tval_read(env, ri, GTIMER_HYP);
}
static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_tval_write(env, ri, GTIMER_HYP, value);
}
static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
gt_ctl_write(env, ri, GTIMER_HYP, value);
}
void arm_gt_ptimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
@ -1250,6 +1278,13 @@ void arm_gt_vtimer_cb(void *opaque)
gt_recalc_timer(cpu, GTIMER_VIRT);
}
void arm_gt_htimer_cb(void *opaque)
{
ARMCPU *cpu = opaque;
gt_recalc_timer(cpu, GTIMER_HYP);
}
static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
/* Note that CNTFRQ is purely reads-as-written for the benefit
* of software; writing it doesn't actually change the timer frequency.
@ -2369,6 +2404,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
PL2_RW, 0, NULL, 0 },
{ "CNTVOFF", 15,0,14, 0,4,0, ARM_CP_64BIT | ARM_CP_CONST, 0,
PL2_RW, 0, NULL, 0 },
{ "CNTHP_CVAL_EL2", 0,14,2, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "CNTHP_CVAL", 15,0,14, 0,6,0, 0, ARM_CP_64BIT | ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "CNTHP_TVAL_EL2", 0,14,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "CNTHP_CTL_EL2", 0,14,2, 3,4,1, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
REGINFO_SENTINEL
};
@ -2460,6 +2503,18 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
{ "CNTVOFF", 15,0,14, 0,4,0, 0, ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cntvoff_el2), {0, 0},
NULL, NULL, gt_cntvoff_write },
{ "CNTHP_CVAL_EL2", 0,14,2, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), {0, 0},
NULL, NULL, gt_hyp_cval_write, NULL, raw_write },
{ "CNTHP_CVAL", .15,0,14, 0,6,0, 0, ARM_CP_64BIT | ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), {0, 0},
NULL, NULL, gt_hyp_cval_write, NULL, raw_write },
{ "CNTHP_TVAL_EL2", 0,14,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_IO,
PL2_RW, 0, NULL, 0, 0, {0, 0},
NULL, gt_hyp_tval_read, gt_hyp_tval_write, NULL, NULL, gt_hyp_timer_reset },
{ "CNTHP_CTL_EL2", 0,14,2, 3,4,1, ARM_CP_STATE_BOTH, ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl), {0, 0},
NULL, NULL, gt_hyp_ctl_write, NULL, raw_write },
#endif
REGINFO_SENTINEL
};

1
qemu/x86_64.h
View file

@ -150,6 +150,7 @@
#define arm_gen_test_cc arm_gen_test_cc_x86_64
#define arm_gt_ptimer_cb arm_gt_ptimer_cb_x86_64
#define arm_gt_vtimer_cb arm_gt_vtimer_cb_x86_64
#define arm_gt_htimer_cb arm_gt_htimer_cb_x86_64
#define arm_handle_psci_call arm_handle_psci_call_x86_64
#define arm_is_psci_call arm_is_psci_call_x86_64
#define arm_is_secure arm_is_secure_x86_64