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target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset

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When the PMSAv7 implementation was originally added it was for R profile
CPUs only, and reset was handled using the cpreg .resetfn hooks.
Unfortunately for M profile cores this doesn't work, because they do
not register any cpregs. Move the reset handling into arm_cpu_reset(),
where it will work for both R profile and M profile cores.

Backports commit 69ceea64bf565559a2b865ffb2a097d2caab805b from qemu
This commit is contained in:
Peter Maydell 2018-03-04 01:20:51 -05:00 committed by Lioncash
parent 6add2f0f65
commit d72175d671
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 22 additions and 16 deletions
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14
qemu/target/arm/cpu.c
View file

@ -235,6 +235,20 @@ static void arm_cpu_reset(CPUState *s)
env->vfp.xregs[ARM_VFP_FPEXC] = 0; env->vfp.xregs[ARM_VFP_FPEXC] = 0;
#endif #endif
if (arm_feature(env, ARM_FEATURE_PMSA) &&
arm_feature(env, ARM_FEATURE_V7)) {
if (cpu->pmsav7_dregion > 0) {
memset(env->pmsav7.drbar, 0,
sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
memset(env->pmsav7.drsr, 0,
sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
memset(env->pmsav7.dracr, 0,
sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
}
env->pmsav7.rnr = 0;
}
set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_to_zero(1, &env->vfp.standard_fp_status);
set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
set_default_nan_mode(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status);

24
qemu/target/arm/helper.c
View file

@ -2166,18 +2166,6 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
*u32p = value; *u32p = value;
} }
static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = arm_env_get_cpu(env);
uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
if (!u32p) {
return;
}
memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
}
static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
@ -2195,18 +2183,22 @@ static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
} }
static const ARMCPRegInfo pmsav7_cp_reginfo[] = { static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
/* Reset for all these registers is handled in arm_cpu_reset(),
* because the PMSAv7 is also used by M-profile CPUs, which do
* not register cpregs but still need the state to be reset.
*/
{ "DRBAR", 15,6,1, 0,0,0, 0,ARM_CP_NO_RAW, { "DRBAR", 15,6,1, 0,0,0, 0,ARM_CP_NO_RAW,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drbar), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drbar), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset }, NULL, pmsav7_read, pmsav7_write, NULL, NULL, arm_cp_reset_ignore },
{ "DRSR", 15,6,1, 0,0,2, 0,ARM_CP_NO_RAW, { "DRSR", 15,6,1, 0,0,2, 0,ARM_CP_NO_RAW,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drsr), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drsr), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset }, NULL, pmsav7_read, pmsav7_write, NULL, NULL, arm_cp_reset_ignore },
{ "DRACR", 15,6,1, 0,0,4, 0,ARM_CP_NO_RAW, { "DRACR", 15,6,1, 0,0,4, 0,ARM_CP_NO_RAW,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset }, NULL, pmsav7_read, pmsav7_write, NULL, NULL, arm_cp_reset_ignore },
{ "RGNR", 15,6,2, 0,0,0, 0,0, { "RGNR", 15,6,2, 0,0,0, 0,0,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.rnr), {0, 0},
NULL, NULL, pmsav7_rgnr_write }, NULL, NULL, pmsav7_rgnr_write, NULL, NULL, arm_cp_reset_ignore },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };