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target/mips: Add emulation of nanoMIPS 48-bit instructions
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and SWPC48 instructions. Backports commit 7ef009b2dd72852505c7348c0bd1f8eb1e62a064 from qemu
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@ -17064,7 +17064,71 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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}
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break;
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case NM_P48I:
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return 6;
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{
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insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
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target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16;
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switch (extract32(ctx->opcode, 16, 5)) {
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case NM_LI48:
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if (rt != 0) {
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], addr_off);
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}
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break;
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case NM_ADDIU48:
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if (rt != 0) {
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tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[rt], addr_off);
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tcg_gen_ext32s_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[rt]);
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}
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break;
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case NM_ADDIUGP48:
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if (rt != 0) {
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gen_op_addr_addi(ctx, tcg_ctx->cpu_gpr[rt], tcg_ctx->cpu_gpr[28], addr_off);
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}
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break;
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case NM_ADDIUPC48:
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if (rt != 0) {
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target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
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addr_off);
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], addr);
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}
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break;
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case NM_LWPC48:
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if (rt != 0) {
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TCGv t0;
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t0 = tcg_temp_new(tcg_ctx);
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target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
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addr_off);
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tcg_gen_movi_tl(tcg_ctx, t0, addr);
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tcg_gen_qemu_ld_tl(ctx->uc, tcg_ctx->cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
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tcg_temp_free(tcg_ctx, t0);
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}
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break;
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case NM_SWPC48:
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
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addr_off);
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tcg_gen_movi_tl(tcg_ctx, t0, addr);
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gen_load_gpr(ctx, t1, rt);
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tcg_gen_qemu_st_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_TEUL);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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}
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break;
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default:
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generate_exception_end(ctx, EXCP_RI);
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break;
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}
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return 6;
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}
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case NM_P_U12:
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switch (extract32(ctx->opcode, 12, 4)) {
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case NM_ORI:
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