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target/arm: Split out gen_gvec_ool_zz

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Backports 40e32e5a8a379baf6e0d49d83cf19950cfbaf96b
This commit is contained in:
Richard Henderson 2021-02-26 14:31:17 -05:00 committed by Lioncash
parent 5bd98feed9
commit da41a23a1b
1 changed files with 13 additions and 10 deletions
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23
qemu/target/arm/translate-sve.c
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@ -139,6 +139,17 @@ static int pred_gvec_reg_size(DisasContext *s)
return size_for_gvec(pred_full_reg_size(s)); return size_for_gvec(pred_full_reg_size(s));
} }
/* Invoke an out-of-line helper on 2 Zregs. */
static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
int rd, int rn, int data)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_2_ool(tcg_ctx, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vsz, vsz, data, fn);
}
/* Invoke an out-of-line helper on 3 Zregs. */ /* Invoke an out-of-line helper on 3 Zregs. */
static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn, static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
int rd, int rn, int rm, int data) int rd, int rn, int rm, int data)
@ -1040,11 +1051,7 @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
return false; return false;
} }
if (sve_access_check(s)) { if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx; gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_2_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vsz, vsz, 0, fns[a->esz]);
} }
return true; return true;
} }
@ -2120,11 +2127,7 @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
}; };
if (sve_access_check(s)) { if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx; gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_2_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vsz, vsz, 0, fns[a->esz]);
} }
return true; return true;
} }