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tcg: Use CPUClass::tlb_fill in cputlb.c

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We can now use the CPUClass hook instead of a named function.

Create a static tlb_fill function to avoid other changes within
cputlb.c. This also isolates the asserts within. Remove the
named tlb_fill function from all of the targets.

Backports commit c319dc13579a92937bffe02ad2c9f1a550e73973 from qemu
This commit is contained in:
Richard Henderson 2019-05-16 17:32:00 -04:00 committed by Lioncash
parent 5d83199931
commit dab0061a0d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
24 changed files with 19 additions and 66 deletions
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1
qemu/aarch64.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_aarch64
#define tlb_add_large_page tlb_add_large_page_aarch64
#define tlb_init tlb_init_aarch64
#define tlb_fill tlb_fill_aarch64
#define tlb_flush tlb_flush_aarch64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
#define tlb_flush_entry tlb_flush_entry_aarch64

1
qemu/aarch64eb.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_aarch64eb
#define tlb_add_large_page tlb_add_large_page_aarch64eb
#define tlb_init tlb_init_aarch64eb
#define tlb_fill tlb_fill_aarch64eb
#define tlb_flush tlb_flush_aarch64eb
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb
#define tlb_flush_entry tlb_flush_entry_aarch64eb

19
qemu/accel/tcg/cputlb.c
View file

@ -472,6 +472,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(struct uc_struct *uc, vo
return ram_addr;
}
/*
* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
* be discarded and looked up again (e.g. via tlb_entry()).
*/
static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu);
bool ok;
/*
* This is not a probe, so only valid return is success; failure
* should result in exception + longjmp to the cpu loop.
*/
ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
assert(ok);
}
/* NOTE: this function can trigger an exception */
/* NOTE2: the returned address is not exactly the physical address: it
* is actually a ram_addr_t (in system mode; the user mode emulation

1
qemu/arm.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_arm
#define tlb_add_large_page tlb_add_large_page_arm
#define tlb_init tlb_init_arm
#define tlb_fill tlb_fill_arm
#define tlb_flush tlb_flush_arm
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm
#define tlb_flush_entry tlb_flush_entry_arm

1
qemu/armeb.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_armeb
#define tlb_add_large_page tlb_add_large_page_armeb
#define tlb_init tlb_init_armeb
#define tlb_fill tlb_fill_armeb
#define tlb_flush tlb_flush_armeb
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb
#define tlb_flush_entry tlb_flush_entry_armeb

1
qemu/header_gen.py
View file

@ -3239,7 +3239,6 @@ symbols = (
'ti925t_initfn',
'tlb_add_large_page',
'tlb_init',
'tlb_fill',
'tlb_flush',
'tlb_flush_by_mmuidx',
'tlb_flush_entry',

8
qemu/include/exec/exec-all.h
View file

@ -353,14 +353,6 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
*/
struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
hwaddr index, MemTxAttrs attrs);
/*
* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
* be discarded and looked up again (e.g. via tlb_entry()).
*/
void tlb_fill(CPUState *cpu, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
#endif
#if defined(CONFIG_USER_ONLY)

1
qemu/m68k.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_m68k
#define tlb_add_large_page tlb_add_large_page_m68k
#define tlb_init tlb_init_m68k
#define tlb_fill tlb_fill_m68k
#define tlb_flush tlb_flush_m68k
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k
#define tlb_flush_entry tlb_flush_entry_m68k

1
qemu/mips.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_mips
#define tlb_add_large_page tlb_add_large_page_mips
#define tlb_init tlb_init_mips
#define tlb_fill tlb_fill_mips
#define tlb_flush tlb_flush_mips
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips
#define tlb_flush_entry tlb_flush_entry_mips

1
qemu/mips64.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_mips64
#define tlb_add_large_page tlb_add_large_page_mips64
#define tlb_init tlb_init_mips64
#define tlb_fill tlb_fill_mips64
#define tlb_flush tlb_flush_mips64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64
#define tlb_flush_entry tlb_flush_entry_mips64

1
qemu/mips64el.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_mips64el
#define tlb_add_large_page tlb_add_large_page_mips64el
#define tlb_init tlb_init_mips64el
#define tlb_fill tlb_fill_mips64el
#define tlb_flush tlb_flush_mips64el
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el
#define tlb_flush_entry tlb_flush_entry_mips64el

1
qemu/mipsel.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_mipsel
#define tlb_add_large_page tlb_add_large_page_mipsel
#define tlb_init tlb_init_mipsel
#define tlb_fill tlb_fill_mipsel
#define tlb_flush tlb_flush_mipsel
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel
#define tlb_flush_entry tlb_flush_entry_mipsel

1
qemu/powerpc.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_powerpc
#define tlb_add_large_page tlb_add_large_page_powerpc
#define tlb_init tlb_init_powerpc
#define tlb_fill tlb_fill_powerpc
#define tlb_flush tlb_flush_powerpc
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc
#define tlb_flush_entry tlb_flush_entry_powerpc

1
qemu/riscv32.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_riscv32
#define tlb_add_large_page tlb_add_large_page_riscv32
#define tlb_init tlb_init_riscv32
#define tlb_fill tlb_fill_riscv32
#define tlb_flush tlb_flush_riscv32
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv32
#define tlb_flush_entry tlb_flush_entry_riscv32

1
qemu/riscv64.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_riscv64
#define tlb_add_large_page tlb_add_large_page_riscv64
#define tlb_init tlb_init_riscv64
#define tlb_fill tlb_fill_riscv64
#define tlb_flush tlb_flush_riscv64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv64
#define tlb_flush_entry tlb_flush_entry_riscv64

1
qemu/sparc.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_sparc
#define tlb_add_large_page tlb_add_large_page_sparc
#define tlb_init tlb_init_sparc
#define tlb_fill tlb_fill_sparc
#define tlb_flush tlb_flush_sparc
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc
#define tlb_flush_entry tlb_flush_entry_sparc

1
qemu/sparc64.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_sparc64
#define tlb_add_large_page tlb_add_large_page_sparc64
#define tlb_init tlb_init_sparc64
#define tlb_fill tlb_fill_sparc64
#define tlb_flush tlb_flush_sparc64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64
#define tlb_flush_entry tlb_flush_entry_sparc64

8
qemu/target/arm/helper.c
View file

@ -12891,14 +12891,6 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#endif
}
#ifndef CONFIG_USER_ONLY
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
#endif
void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
{
/* Implement DC ZVA, which zeroes a fixed-length block of memory.

8
qemu/target/i386/excp_helper.c
View file

@ -702,11 +702,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
return true;
#endif
}
#if !defined(CONFIG_USER_ONLY)
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
#endif

8
qemu/target/m68k/helper.c
View file

@ -530,14 +530,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
cpu_loop_exit_restore(cs, retaddr);
}
#ifndef CONFIG_USER_ONLY
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
#endif
uint32_t HELPER(bitrev)(uint32_t x)
{
x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);

6
qemu/target/mips/helper.c
View file

@ -931,12 +931,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
#ifndef CONFIG_USER_ONLY
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
{
hwaddr physical;

6
qemu/target/riscv/cpu_helper.c
View file

@ -379,12 +379,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
#endif
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,

6
qemu/target/sparc/ldst_helper.c
View file

@ -1929,10 +1929,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
#endif
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
}
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
#endif

1
qemu/x86_64.h
View file

@ -3233,7 +3233,6 @@
#define ti925t_initfn ti925t_initfn_x86_64
#define tlb_add_large_page tlb_add_large_page_x86_64
#define tlb_init tlb_init_x86_64
#define tlb_fill tlb_fill_x86_64
#define tlb_flush tlb_flush_x86_64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64
#define tlb_flush_entry tlb_flush_entry_x86_64