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tcg: Use CPUClass::tlb_fill in cputlb.c
We can now use the CPUClass hook instead of a named function. Create a static tlb_fill function to avoid other changes within cputlb.c. This also isolates the asserts within. Remove the named tlb_fill function from all of the targets. Backports commit c319dc13579a92937bffe02ad2c9f1a550e73973 from qemu
This commit is contained in:
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5d83199931
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_aarch64
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#define ti925t_initfn ti925t_initfn_aarch64
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#define tlb_add_large_page tlb_add_large_page_aarch64
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#define tlb_add_large_page tlb_add_large_page_aarch64
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#define tlb_init tlb_init_aarch64
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#define tlb_init tlb_init_aarch64
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#define tlb_fill tlb_fill_aarch64
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#define tlb_flush tlb_flush_aarch64
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#define tlb_flush tlb_flush_aarch64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
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#define tlb_flush_entry tlb_flush_entry_aarch64
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#define tlb_flush_entry tlb_flush_entry_aarch64
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_aarch64eb
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#define ti925t_initfn ti925t_initfn_aarch64eb
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#define tlb_add_large_page tlb_add_large_page_aarch64eb
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#define tlb_add_large_page tlb_add_large_page_aarch64eb
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#define tlb_init tlb_init_aarch64eb
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#define tlb_init tlb_init_aarch64eb
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#define tlb_fill tlb_fill_aarch64eb
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#define tlb_flush tlb_flush_aarch64eb
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#define tlb_flush tlb_flush_aarch64eb
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb
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#define tlb_flush_entry tlb_flush_entry_aarch64eb
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#define tlb_flush_entry tlb_flush_entry_aarch64eb
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@ -472,6 +472,25 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(struct uc_struct *uc, vo
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return ram_addr;
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return ram_addr;
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}
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}
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/*
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* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
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* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
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* be discarded and looked up again (e.g. via tlb_entry()).
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*/
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static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu);
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bool ok;
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/*
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* This is not a probe, so only valid return is success; failure
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* should result in exception + longjmp to the cpu loop.
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*/
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ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
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assert(ok);
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}
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/* NOTE: this function can trigger an exception */
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/* NOTE: this function can trigger an exception */
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/* NOTE2: the returned address is not exactly the physical address: it
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/* NOTE2: the returned address is not exactly the physical address: it
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* is actually a ram_addr_t (in system mode; the user mode emulation
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* is actually a ram_addr_t (in system mode; the user mode emulation
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_arm
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#define ti925t_initfn ti925t_initfn_arm
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#define tlb_add_large_page tlb_add_large_page_arm
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#define tlb_add_large_page tlb_add_large_page_arm
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#define tlb_init tlb_init_arm
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#define tlb_init tlb_init_arm
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#define tlb_fill tlb_fill_arm
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#define tlb_flush tlb_flush_arm
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#define tlb_flush tlb_flush_arm
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm
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#define tlb_flush_entry tlb_flush_entry_arm
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#define tlb_flush_entry tlb_flush_entry_arm
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_armeb
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#define ti925t_initfn ti925t_initfn_armeb
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#define tlb_add_large_page tlb_add_large_page_armeb
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#define tlb_add_large_page tlb_add_large_page_armeb
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#define tlb_init tlb_init_armeb
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#define tlb_init tlb_init_armeb
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#define tlb_fill tlb_fill_armeb
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#define tlb_flush tlb_flush_armeb
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#define tlb_flush tlb_flush_armeb
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb
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#define tlb_flush_entry tlb_flush_entry_armeb
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#define tlb_flush_entry tlb_flush_entry_armeb
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@ -3239,7 +3239,6 @@ symbols = (
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'ti925t_initfn',
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'ti925t_initfn',
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'tlb_add_large_page',
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'tlb_add_large_page',
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'tlb_init',
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'tlb_init',
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'tlb_fill',
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'tlb_flush',
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'tlb_flush',
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'tlb_flush_by_mmuidx',
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'tlb_flush_by_mmuidx',
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'tlb_flush_entry',
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'tlb_flush_entry',
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@ -353,14 +353,6 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
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*/
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*/
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struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
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struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
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hwaddr index, MemTxAttrs attrs);
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hwaddr index, MemTxAttrs attrs);
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/*
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* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
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* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
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* be discarded and looked up again (e.g. via tlb_entry()).
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*/
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void tlb_fill(CPUState *cpu, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
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#endif
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#endif
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#if defined(CONFIG_USER_ONLY)
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#if defined(CONFIG_USER_ONLY)
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_m68k
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#define ti925t_initfn ti925t_initfn_m68k
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#define tlb_add_large_page tlb_add_large_page_m68k
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#define tlb_add_large_page tlb_add_large_page_m68k
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#define tlb_init tlb_init_m68k
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#define tlb_init tlb_init_m68k
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#define tlb_fill tlb_fill_m68k
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#define tlb_flush tlb_flush_m68k
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#define tlb_flush tlb_flush_m68k
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k
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#define tlb_flush_entry tlb_flush_entry_m68k
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#define tlb_flush_entry tlb_flush_entry_m68k
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_mips
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#define ti925t_initfn ti925t_initfn_mips
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#define tlb_add_large_page tlb_add_large_page_mips
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#define tlb_add_large_page tlb_add_large_page_mips
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#define tlb_init tlb_init_mips
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#define tlb_init tlb_init_mips
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#define tlb_fill tlb_fill_mips
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#define tlb_flush tlb_flush_mips
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#define tlb_flush tlb_flush_mips
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips
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#define tlb_flush_entry tlb_flush_entry_mips
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#define tlb_flush_entry tlb_flush_entry_mips
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_mips64
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#define ti925t_initfn ti925t_initfn_mips64
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#define tlb_add_large_page tlb_add_large_page_mips64
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#define tlb_add_large_page tlb_add_large_page_mips64
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#define tlb_init tlb_init_mips64
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#define tlb_init tlb_init_mips64
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#define tlb_fill tlb_fill_mips64
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#define tlb_flush tlb_flush_mips64
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#define tlb_flush tlb_flush_mips64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64
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#define tlb_flush_entry tlb_flush_entry_mips64
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#define tlb_flush_entry tlb_flush_entry_mips64
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_mips64el
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#define ti925t_initfn ti925t_initfn_mips64el
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#define tlb_add_large_page tlb_add_large_page_mips64el
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#define tlb_add_large_page tlb_add_large_page_mips64el
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#define tlb_init tlb_init_mips64el
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#define tlb_init tlb_init_mips64el
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#define tlb_fill tlb_fill_mips64el
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#define tlb_flush tlb_flush_mips64el
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#define tlb_flush tlb_flush_mips64el
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el
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#define tlb_flush_entry tlb_flush_entry_mips64el
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#define tlb_flush_entry tlb_flush_entry_mips64el
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_mipsel
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#define ti925t_initfn ti925t_initfn_mipsel
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#define tlb_add_large_page tlb_add_large_page_mipsel
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#define tlb_add_large_page tlb_add_large_page_mipsel
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#define tlb_init tlb_init_mipsel
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#define tlb_init tlb_init_mipsel
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#define tlb_fill tlb_fill_mipsel
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#define tlb_flush tlb_flush_mipsel
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#define tlb_flush tlb_flush_mipsel
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel
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#define tlb_flush_entry tlb_flush_entry_mipsel
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#define tlb_flush_entry tlb_flush_entry_mipsel
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_powerpc
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#define ti925t_initfn ti925t_initfn_powerpc
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#define tlb_add_large_page tlb_add_large_page_powerpc
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#define tlb_add_large_page tlb_add_large_page_powerpc
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#define tlb_init tlb_init_powerpc
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#define tlb_init tlb_init_powerpc
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#define tlb_fill tlb_fill_powerpc
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#define tlb_flush tlb_flush_powerpc
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#define tlb_flush tlb_flush_powerpc
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc
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#define tlb_flush_entry tlb_flush_entry_powerpc
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#define tlb_flush_entry tlb_flush_entry_powerpc
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_riscv32
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#define ti925t_initfn ti925t_initfn_riscv32
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#define tlb_add_large_page tlb_add_large_page_riscv32
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#define tlb_add_large_page tlb_add_large_page_riscv32
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#define tlb_init tlb_init_riscv32
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#define tlb_init tlb_init_riscv32
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#define tlb_fill tlb_fill_riscv32
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#define tlb_flush tlb_flush_riscv32
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#define tlb_flush tlb_flush_riscv32
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv32
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv32
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#define tlb_flush_entry tlb_flush_entry_riscv32
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#define tlb_flush_entry tlb_flush_entry_riscv32
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@ -3233,7 +3233,6 @@
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#define ti925t_initfn ti925t_initfn_riscv64
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#define ti925t_initfn ti925t_initfn_riscv64
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#define tlb_add_large_page tlb_add_large_page_riscv64
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#define tlb_add_large_page tlb_add_large_page_riscv64
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#define tlb_init tlb_init_riscv64
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#define tlb_init tlb_init_riscv64
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#define tlb_fill tlb_fill_riscv64
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#define tlb_flush tlb_flush_riscv64
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#define tlb_flush tlb_flush_riscv64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv64
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#define tlb_flush_entry tlb_flush_entry_riscv64
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#define tlb_flush_entry tlb_flush_entry_riscv64
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#define ti925t_initfn ti925t_initfn_sparc
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#define ti925t_initfn ti925t_initfn_sparc
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#define tlb_add_large_page tlb_add_large_page_sparc
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#define tlb_add_large_page tlb_add_large_page_sparc
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#define tlb_init tlb_init_sparc
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#define tlb_init tlb_init_sparc
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#define tlb_fill tlb_fill_sparc
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#define tlb_flush tlb_flush_sparc
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#define tlb_flush tlb_flush_sparc
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc
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#define tlb_flush_entry tlb_flush_entry_sparc
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#define tlb_flush_entry tlb_flush_entry_sparc
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#define ti925t_initfn ti925t_initfn_sparc64
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#define ti925t_initfn ti925t_initfn_sparc64
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#define tlb_add_large_page tlb_add_large_page_sparc64
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#define tlb_add_large_page tlb_add_large_page_sparc64
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#define tlb_init tlb_init_sparc64
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#define tlb_init tlb_init_sparc64
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#define tlb_fill tlb_fill_sparc64
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#define tlb_flush tlb_flush_sparc64
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#define tlb_flush tlb_flush_sparc64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64
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#define tlb_flush_entry tlb_flush_entry_sparc64
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#define tlb_flush_entry tlb_flush_entry_sparc64
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#endif
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#endif
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}
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}
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#ifndef CONFIG_USER_ONLY
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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arm_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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#endif
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void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
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void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
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{
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{
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/* Implement DC ZVA, which zeroes a fixed-length block of memory.
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/* Implement DC ZVA, which zeroes a fixed-length block of memory.
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@ -702,11 +702,3 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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return true;
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return true;
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#endif
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#endif
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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x86_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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#endif
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@ -530,14 +530,6 @@ bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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cpu_loop_exit_restore(cs, retaddr);
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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#ifndef CONFIG_USER_ONLY
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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m68k_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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#endif
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uint32_t HELPER(bitrev)(uint32_t x)
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uint32_t HELPER(bitrev)(uint32_t x)
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{
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{
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x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);
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x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);
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@ -931,12 +931,6 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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}
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}
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
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}
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hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
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hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
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{
|
{
|
||||||
hwaddr physical;
|
hwaddr physical;
|
||||||
|
|
|
@ -379,12 +379,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
||||||
env->badaddr = addr;
|
env->badaddr = addr;
|
||||||
riscv_raise_exception(env, cs->exception_index, retaddr);
|
riscv_raise_exception(env, cs->exception_index, retaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
void tlb_fill(CPUState *cs, target_ulong addr, int size,
|
|
||||||
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
|
|
||||||
{
|
|
||||||
riscv_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
||||||
|
|
|
@ -1929,10 +1929,4 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
|
||||||
#endif
|
#endif
|
||||||
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
|
cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
void tlb_fill(CPUState *cs, target_ulong addr, int size,
|
|
||||||
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
|
|
||||||
{
|
|
||||||
sparc_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -3233,7 +3233,6 @@
|
||||||
#define ti925t_initfn ti925t_initfn_x86_64
|
#define ti925t_initfn ti925t_initfn_x86_64
|
||||||
#define tlb_add_large_page tlb_add_large_page_x86_64
|
#define tlb_add_large_page tlb_add_large_page_x86_64
|
||||||
#define tlb_init tlb_init_x86_64
|
#define tlb_init tlb_init_x86_64
|
||||||
#define tlb_fill tlb_fill_x86_64
|
|
||||||
#define tlb_flush tlb_flush_x86_64
|
#define tlb_flush tlb_flush_x86_64
|
||||||
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64
|
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64
|
||||||
#define tlb_flush_entry tlb_flush_entry_x86_64
|
#define tlb_flush_entry tlb_flush_entry_x86_64
|
||||||
|
|
Loading…
Reference in a new issue