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target-arm: rename c1_coproc to cpacr_el1

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Rename the field holding CPACR_EL1 system register state in AArch64
naming style.

Backports commit 7ebd5f2e03a00889619bb97e83062d27066d4a26 from qemu
This commit is contained in:
Sergey Fedorov 2018-02-12 20:44:07 -05:00 committed by Lioncash
parent e1a7c13fb4
commit dd9e33bb6d
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GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 8 additions and 8 deletions
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4
qemu/target-arm/cpu.c
View file

@ -107,7 +107,7 @@ static void arm_cpu_reset(CPUState *s)
/* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
/* and to the FP/Neon instructions */
env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
#else
/* Reset into the highest available EL */
if (arm_feature(env, ARM_FEATURE_EL3)) {
@ -122,7 +122,7 @@ static void arm_cpu_reset(CPUState *s)
} else {
#if defined(CONFIG_USER_ONLY)
/* Userspace expects access to cp10 and cp11 for FP/Neon */
env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
#endif
}

4
qemu/target-arm/cpu.h
View file

@ -205,7 +205,7 @@ typedef struct CPUARMState {
};
uint64_t sctlr_el[4];
};
uint64_t c1_coproc; /* Coprocessor access register. */
uint64_t cpacr_el1; /* Architectural feature access control register */
uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint64_t sder; /* Secure debug enable register. */
uint32_t nsacr; /* Non-secure access control register. */
@ -1838,7 +1838,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
int fpen;
if (arm_feature(env, ARM_FEATURE_V6)) {
fpen = extract32(env->cp15.c1_coproc, 20, 2);
fpen = extract32(env->cp15.cpacr_el1, 20, 2);
} else {
/* CPACR doesn't exist before v6, so VFP is always accessible */
fpen = 3;

4
qemu/target-arm/helper.c
View file

@ -473,7 +473,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
value &= mask;
}
env->cp15.c1_coproc = value;
env->cp15.cpacr_el1 = value;
}
static const ARMCPRegInfo v6_cp_reginfo[] = {
@ -495,7 +495,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
{ "WFAR", 15,6,0, 0,0,1, 0,
ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
{ "CPACR", 0,1,0, 3,0,2, ARM_CP_STATE_BOTH,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c1_coproc), {0, 0},
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cpacr_el1), {0, 0},
NULL, NULL, cpacr_write },
REGINFO_SENTINEL
};

4
qemu/target-arm/unicorn_aarch64.c
View file

@ -77,7 +77,7 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
switch(regid) {
default: break;
case UC_ARM64_REG_CPACR_EL1:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1;
break;
case UC_ARM64_REG_ESR:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
@ -154,7 +154,7 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
switch(regid) {
default: break;
case UC_ARM64_REG_CPACR_EL1:
ARM_CPU(uc, mycpu)->env.cp15.c1_coproc = *(uint32_t *)value;
ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1 = *(uint32_t *)value;
break;
case UC_ARM64_REG_TPIDR_EL0:
ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[0] = *(uint64_t *)value;