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target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks

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Section D6.7 of the ARM ARM states:

For the purpose of determining Tag Check Fault handling, unprivileged
load and store instructions are treated as if executed at EL0 when
executed at either:
- EL1, when the Effective value of PSTATE.UAO is 0.
- EL2, when both the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}
and the Effective value of PSTATE.UAO is 0.

ARM has confirmed a defect in the pseudocode function
AArch64.TagCheckFault that makes it inconsistent with the above
wording. The remedy is to adjust references to PSTATE.EL in that
function to instead refer to AArch64.AccessUsesEL(acctype), so
that unprivileged instructions use SCTLR_EL1.TCF0 and TFSRE0_EL1.
The exception type for synchronous tag check faults remains unchanged.

This patch implements the described change by partially reverting
commits 50244cc76abc and cc97b0019bb5.

Backports 2d928adf8a9148510e1b2041145b8a873f4d26df
This commit is contained in:
Peter Collingbourne 2021-03-08 11:33:54 -05:00 committed by Lioncash
parent 03c8d3ff00
commit de7bcbae57
2 changed files with 10 additions and 5 deletions
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2
qemu/target/arm/helper.c
View file

@ -12795,7 +12795,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV) if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
&& tbid && tbid
&& !(env->pstate & PSTATE_TCO) && !(env->pstate & PSTATE_TCO)
&& (sctlr & SCTLR_TCF) && (sctlr & SCTLR_TCF0)
&& allocation_tag_access_enabled(env, 0, sctlr)) { && allocation_tag_access_enabled(env, 0, sctlr)) {
flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1); flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
} }

13
qemu/target/arm/mte_helper.c
View file

@ -526,10 +526,14 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
reg_el = regime_el(env, arm_mmu_idx); reg_el = regime_el(env, arm_mmu_idx);
sctlr = env->cp15.sctlr_el[reg_el]; sctlr = env->cp15.sctlr_el[reg_el];
el = arm_current_el(env); switch (arm_mmu_idx) {
if (el == 0) { case ARMMMUIdx_E10_0:
case ARMMMUIdx_E20_0:
el = 0;
tcf = extract64(sctlr, 38, 2); tcf = extract64(sctlr, 38, 2);
} else { break;
default:
el = reg_el;
tcf = extract64(sctlr, 40, 2); tcf = extract64(sctlr, 40, 2);
} }
@ -545,7 +549,8 @@ static void mte_check_fail(CPUARMState *env, uint32_t desc,
cpu_restore_state(env_cpu(env), ra, true); cpu_restore_state(env_cpu(env), ra, true);
env->exception.vaddress = dirty_ptr; env->exception.vaddress = dirty_ptr;
is_write = FIELD_EX32(desc, MTEDESC, WRITE); is_write = FIELD_EX32(desc, MTEDESC, WRITE);
syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11); syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0,
is_write, 0x11);
raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env)); raise_exception(env, EXCP_DATA_ABORT, syn, exception_target_el(env));
/* noreturn, but fall through to the assert anyway */ /* noreturn, but fall through to the assert anyway */