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target/arm/translate-a64: Don't underdecode SIMD ld/st single

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In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.

Backports commit 9c72b68ad746a51f63822cffab4d144b5957823a from qemu
This commit is contained in:
Peter Maydell 2019-02-03 17:36:56 -05:00 committed by Lioncash
parent 60ccaf56ac
commit decebb5936
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 1 deletions
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11
qemu/target/arm/translate-a64.c
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@ -3483,6 +3483,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
int rt = extract32(insn, 0, 5); int rt = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5); int rn = extract32(insn, 5, 5);
int rm = extract32(insn, 16, 5);
int size = extract32(insn, 10, 2); int size = extract32(insn, 10, 2);
int S = extract32(insn, 12, 1); int S = extract32(insn, 12, 1);
int opc = extract32(insn, 13, 3); int opc = extract32(insn, 13, 3);
@ -3498,6 +3499,15 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
int ebytes, xs; int ebytes, xs;
TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes;
if (extract32(insn, 31, 1)) {
unallocated_encoding(s);
return;
}
if (!is_postidx && rm != 0) {
unallocated_encoding(s);
return;
}
switch (scale) { switch (scale) {
case 3: case 3:
if (!is_load || S) { if (!is_load || S) {
@ -3575,7 +3585,6 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
} }
if (is_postidx) { if (is_postidx) {
int rm = extract32(insn, 16, 5);
if (rm == 31) { if (rm == 31) {
tcg_gen_mov_i64(tcg_ctx, tcg_rn, tcg_addr); tcg_gen_mov_i64(tcg_ctx, tcg_rn, tcg_addr);
} else { } else {