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target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

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Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Backports commit ca6c7803d2beae43299a80f4549d36579881fc0b from qemu
This commit is contained in:
Petar Jovanovic 2018-02-15 15:42:18 -05:00 committed by Lioncash
parent afb48e9fc5
commit dfa3d51a0f
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 4 deletions
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6
qemu/target-mips/translate.c
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@ -9375,7 +9375,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.s";
break;
case OPC_RECIP_S:
check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
@ -9387,7 +9386,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.s";
break;
case OPC_RSQRT_S:
check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
@ -9920,7 +9918,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.d";
break;
case OPC_RECIP_D:
check_cp1_64bitmode(ctx);
check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
@ -9932,7 +9930,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.d";
break;
case OPC_RSQRT_D:
check_cp1_64bitmode(ctx);
check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);