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target/arm/translate.c: Delete/amend incorrect comments

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In arm_tr_init_disas_context() we have a FIXME comment that suggests
"cpu_M0 can probably be the same as cpu_V0". This isn't in fact
possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(),
and that function is called in various places where cpu_M0 contains a
live value (i.e. between gen_op_iwmmxt_movq_M0_wRn() and
gen_op_iwmmxt_movq_wRn_M0() calls). Remove the comment.

We also have a comment on the declarations of cpu_V0/V1/M0 which
claims they're "for efficiency". This isn't true with modern TCG, so
replace this comment with one which notes that they're only used with
the iwmmxt decode

Backports 8b4c9a50dc9531a729ae4b5941d287ad0422db48
This commit is contained in:
Peter Maydell 2021-02-26 11:23:51 -05:00 committed by Lioncash
parent 0759bb8eaf
commit e0000d1700
3 changed files with 1 additions and 2 deletions
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1
qemu/target/arm/translate.c
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@ -8827,7 +8827,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->V0 = tcg_temp_new_i64(tcg_ctx);
dc->V1 = tcg_temp_new_i64(tcg_ctx);
/* FIXME: dc->M0 can probably be the same as dc->V0. */
dc->M0 = tcg_temp_new_i64(tcg_ctx);
}

1
qemu/target/arm/translate.h
View file

@ -103,6 +103,7 @@ typedef struct DisasContext {
TCGv_i64 tmp_a64[TMP_A64_MAX];
// Unicorn: Moved here to avoid global state.
/* These are TCG temporaries used only by the legacy iwMMXt decoder */
TCGv_i64 V0;
TCGv_i64 V1;
TCGv_i64 M0;

1
qemu/tcg/tcg.h
View file

@ -810,7 +810,6 @@ struct TCGContext {
TCGv store_dummy;
/* qemu/target-arm/translate.c */
/* We reuse the same 64-bit temporaries for efficiency. */
TCGv_i32 cpu_R[16];
TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
TCGv_i64 cpu_exclusive_addr;