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target/mips: Add reset state for PWSize and PWField registers

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Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa

Backports commit 630107955757b9dfc5c09f105caa267eded2e3b1 from qemu
This commit is contained in:
Yongbok Kim 2018-10-23 14:23:53 -04:00 committed by Lioncash
parent a35a59bda6
commit e1ea411300
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 18 additions and 0 deletions
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18
qemu/target/mips/translate.c
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@ -26616,6 +26616,24 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Status |= (1 << CP0St_FR);
}
if (env->insn_flags & ISA_MIPS32R6) {
/* PTW = 1 */
env->CP0_PWSize = 0x40;
/* GDI = 12 */
/* UDI = 12 */
/* MDI = 12 */
/* PRI = 12 */
/* PTEI = 2 */
env->CP0_PWField = 0x0C30C302;
} else {
/* GDI = 0 */
/* UDI = 0 */
/* MDI = 0 */
/* PRI = 0 */
/* PTEI = 2 */
env->CP0_PWField = 0x02;
}
if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
/* microMIPS on reset when Config3.ISA is 3 */
env->hflags |= MIPS_HFLAG_M16;