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target/mips: Clean up handling of CP0 register 15

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Clean up handling of CP0 register 15.

Backports commit 4466cd49e53d3a4418a0f27ea9ff335fd9aed180 from qemu
This commit is contained in:
Aleksandar Markovic 2019-11-18 23:11:44 -05:00 committed by Lioncash
parent 41133450de
commit e54d2617a1
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 11 additions and 10 deletions
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1
qemu/target/mips/cpu.h
View file

@ -366,6 +366,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1

20
qemu/target/mips/translate.c
View file

@ -7302,17 +7302,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
case 0:
case CP0_REG15__PRID:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
case 1:
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
register_name = "EBase";
break;
case 3:
case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@ -8036,11 +8036,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
case 0:
case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
case 1:
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "EBase";
@ -8773,16 +8773,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
case 0:
case CP0_REG15__PRID:
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
case 1:
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
case 3:
case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@ -9492,11 +9492,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
case 0:
case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
case 1:
case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(tcg_ctx, tcg_ctx->cpu_env, arg);
register_name = "EBase";