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tcg: Make cpu_fsr a TCGv

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Lioncash 2018-02-21 01:20:53 -05:00
parent b51f920404
commit e5a776b495
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 21 additions and 22 deletions
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37
qemu/target-sparc/translate.c
View file

@ -1348,49 +1348,49 @@ static void gen_fcompare(DisasContext *dc, DisasCompare *cmp, unsigned int cc, u
gen_op_eval_bn(dc, r_dst); gen_op_eval_bn(dc, r_dst);
break; break;
case 0x1: case 0x1:
gen_op_eval_fbne(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbne(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x2: case 0x2:
gen_op_eval_fblg(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fblg(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x3: case 0x3:
gen_op_eval_fbul(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbul(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x4: case 0x4:
gen_op_eval_fbl(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbl(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x5: case 0x5:
gen_op_eval_fbug(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbug(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x6: case 0x6:
gen_op_eval_fbg(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbg(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x7: case 0x7:
gen_op_eval_fbu(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbu(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0x8: case 0x8:
gen_op_eval_ba(dc, r_dst); gen_op_eval_ba(dc, r_dst);
break; break;
case 0x9: case 0x9:
gen_op_eval_fbe(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbe(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0xa: case 0xa:
gen_op_eval_fbue(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbue(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0xb: case 0xb:
gen_op_eval_fbge(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbge(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0xc: case 0xc:
gen_op_eval_fbuge(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbuge(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0xd: case 0xd:
gen_op_eval_fble(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fble(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0xe: case 0xe:
gen_op_eval_fbule(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbule(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
case 0xf: case 0xf:
gen_op_eval_fbo(dc, r_dst, *(TCGv *)tcg_ctx->cpu_fsr, offset); gen_op_eval_fbo(dc, r_dst, tcg_ctx->cpu_fsr, offset);
break; break;
} }
} }
@ -1724,8 +1724,8 @@ static inline void gen_op_fpexception_im(DisasContext *dc, int fsr_flags)
TCGContext *tcg_ctx = dc->uc->tcg_ctx; TCGContext *tcg_ctx = dc->uc->tcg_ctx;
TCGv_i32 r_const; TCGv_i32 r_const;
tcg_gen_andi_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_fsr, *(TCGv *)tcg_ctx->cpu_fsr, FSR_FTT_NMASK); tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_fsr, FSR_FTT_NMASK);
tcg_gen_ori_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_fsr, *(TCGv *)tcg_ctx->cpu_fsr, fsr_flags); tcg_gen_ori_tl(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_fsr, fsr_flags);
r_const = tcg_const_i32(tcg_ctx, TT_FP_EXCP); r_const = tcg_const_i32(tcg_ctx, TT_FP_EXCP);
gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, r_const); gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, r_const);
tcg_temp_free_i32(tcg_ctx, r_const); tcg_temp_free_i32(tcg_ctx, r_const);
@ -1752,7 +1752,7 @@ static int gen_trap_ifnofpu(DisasContext *dc)
static inline void gen_op_clear_ieee_excp_and_FTT(DisasContext *dc) static inline void gen_op_clear_ieee_excp_and_FTT(DisasContext *dc)
{ {
TCGContext *tcg_ctx = dc->uc->tcg_ctx; TCGContext *tcg_ctx = dc->uc->tcg_ctx;
tcg_gen_andi_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_fsr, *(TCGv *)tcg_ctx->cpu_fsr, FSR_FTT_CEXC_NMASK); tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_fsr, FSR_FTT_CEXC_NMASK);
} }
static inline void gen_fop_FF(DisasContext *dc, int rd, int rs, static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
@ -5600,8 +5600,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
tcg_ctx->cpu_psr = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, psr), tcg_ctx->cpu_psr = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, psr),
"psr"); "psr");
tcg_ctx->cpu_fsr = g_malloc0(sizeof(TCGv)); tcg_ctx->cpu_fsr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fsr),
*((TCGv *)tcg_ctx->cpu_fsr) = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fsr),
"fsr"); "fsr");
tcg_ctx->sparc_cpu_pc = g_malloc0(sizeof(TCGv)); tcg_ctx->sparc_cpu_pc = g_malloc0(sizeof(TCGv));

1
qemu/target-sparc/unicorn.c
View file

@ -38,7 +38,6 @@ void sparc_release(void *ctx)
g_free(tcg_ctx->cpu_cc_src); g_free(tcg_ctx->cpu_cc_src);
g_free(tcg_ctx->cpu_cc_src2); g_free(tcg_ctx->cpu_cc_src2);
g_free(tcg_ctx->cpu_cc_dst); g_free(tcg_ctx->cpu_cc_dst);
g_free(tcg_ctx->cpu_fsr);
g_free(tcg_ctx->sparc_cpu_pc); g_free(tcg_ctx->sparc_cpu_pc);
g_free(tcg_ctx->cpu_npc); g_free(tcg_ctx->cpu_npc);

5
qemu/tcg/tcg.h
View file

@ -832,8 +832,9 @@ struct TCGContext {
/* Floating point registers */ /* Floating point registers */
TCGv_i64 cpu_fpr[32]; // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc TCGv_i64 cpu_fpr[32]; // TARGET_DPREGS = 32 for Sparc64, 16 for Sparc
// void *cpu_cc_src, *cpu_cc_src2, *cpu_cc_dst; TCGv cpu_fsr;
void *cpu_fsr, *sparc_cpu_pc, *cpu_npc; void *sparc_cpu_pc;
void *cpu_npc;
void *cpu_regs_sparc[32]; void *cpu_regs_sparc[32];
TCGv cpu_y; TCGv cpu_y;
TCGv cpu_tbr; TCGv cpu_tbr;