yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-22 13:41:05 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-i386: Use new deposit and extract ops

Browse source 
A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.

Backports commit 04fc2f1c8fc030a11e08e81bb926392c0991282a from qemu
This commit is contained in:
Richard Henderson 2018-03-01 14:35:36 -05:00 committed by Lioncash
parent ce3c153bd8
commit e5acbeb86e
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 23 additions and 22 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

45
qemu/target-i386/translate.c
View file

@ -449,8 +449,7 @@ static inline void gen_op_mov_v_reg(TCGContext *s, TCGMemOp ot, TCGv t0, int reg
TCGv *cpu_regs = s->cpu_regs;
if (ot == MO_8 && byte_reg_is_xH(s->x86_64_hregs, reg)) {
tcg_gen_shri_tl(s, t0, cpu_regs[reg - 4], 8);
tcg_gen_ext8u_tl(s, t0, t0);
tcg_gen_extract_tl(s, t0, cpu_regs[reg - 4], 8, 8);
} else {
tcg_gen_mov_tl(s, t0, cpu_regs[reg]);
}
@ -4336,8 +4335,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
/* Extract the LEN into a mask. Lengths larger than
operand size get all ones. */
tcg_gen_shri_tl(tcg_ctx, cpu_A0, cpu_regs[s->vex_v], 8);
tcg_gen_ext8u_tl(tcg_ctx, cpu_A0, cpu_A0);
tcg_gen_extract_tl(tcg_ctx, cpu_A0, cpu_regs[s->vex_v], 8, 8);
tcg_gen_movcond_tl(tcg_ctx, TCG_COND_LEU, cpu_A0, cpu_A0, bound,
cpu_A0, bound);
tcg_temp_free(tcg_ctx, bound);
@ -4488,9 +4486,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_compute_eflags(s);
}
carry_in = cpu_tmp0;
tcg_gen_shri_tl(tcg_ctx, carry_in, cpu_cc_src,
ctz32(b == 0x1f6 ? CC_C : CC_O));
tcg_gen_andi_tl(tcg_ctx, carry_in, carry_in, 1);
tcg_gen_extract_tl(tcg_ctx, carry_in, cpu_cc_src,
ctz32(b == 0x1f6 ? CC_C : CC_O), 1);
}
switch (ot) {
@ -6102,21 +6099,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
rm = (modrm & 7) | REX_B(s);
if (mod == 3) {
gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
case MO_SB:
tcg_gen_ext8s_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
case MO_UW:
tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
default:
case MO_SW:
tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
if (s_ot == MO_SB && byte_reg_is_xH(tcg_ctx->x86_64_hregs, rm)) {
tcg_gen_sextract_tl(tcg_ctx, cpu_T0, cpu_regs[rm - 4], 8, 8);
} else {
gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm);
switch (s_ot) {
case MO_UB:
tcg_gen_ext8u_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
case MO_SB:
tcg_gen_ext8s_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
case MO_UW:
tcg_gen_ext16u_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
default:
case MO_SW:
tcg_gen_ext16s_tl(tcg_ctx, cpu_T0, cpu_T0);
break;
}
}
gen_op_mov_reg_v(tcg_ctx, d_ot, reg, cpu_T0);
} else {