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target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs

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ARMCPRegInfo structs will default to .cp = 15 if they
are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32
(because a coprocessor number of 0 is valid for AArch32).
We forgot to explicitly set .cp = 15 for the HMAIR1 and
HAMAIR1 regdefs, which meant they would UNDEF when the guest
tried to access them under cp15.

Backports commit b5ede85bfb7ba1a8f6086494c82f400b29969f65 from qemu
This commit is contained in:
Peter Maydell 2018-08-22 12:36:09 -04:00 committed by Lioncash
parent 2d2c6982ce
commit e9fb085aa1
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 4 deletions
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8
qemu/target/arm/helper.c
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@ -3356,11 +3356,11 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
PL2_RW, 0, NULL, 0 },
{ "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
{ "HMAIR1", 15,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "AMAIR_EL2", 0,10,3, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "HAMAIR1", 0,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
{ "HAMAIR1", 15,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "AFSR0_EL2", 0,5,1, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
@ -3463,12 +3463,12 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
cptr_access },
{ "MAIR_EL2", 0,10,2, 3,4,0, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[2]) },
{ "HMAIR1", 0,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_ALIAS,
{ "HMAIR1", 15,10,2, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
{ "AMAIR_EL2", 0,10,3, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
/* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
{ "HAMAIR1", 0,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
{ "HAMAIR1", 15,10,3, 0,4,1, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "AFSR0_EL2", 0,5,1, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },