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target/arm: generalize 2-stage page-walk condition

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The stage_1_mmu_idx() already effectively keeps track of which
translation regimes have two stages. Don't hard-code another test.

Backports 7879460a6149ed5e80c29cac85449191d9c5754a
This commit is contained in:
Rémi Denis-Courmont 2021-03-04 14:26:20 -05:00 committed by Lioncash
parent 07ebb7f7ba
commit eeefc3c4a2
1 changed files with 6 additions and 7 deletions
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13
qemu/target/arm/helper.c
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@ -11880,12 +11880,12 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
target_ulong *page_size, target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{ {
if (mmu_idx == ARMMMUIdx_E10_0 || ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
mmu_idx == ARMMMUIdx_E10_1 ||
mmu_idx == ARMMMUIdx_E10_1_PAN) { if (mmu_idx != s1_mmu_idx) {
/* /*
* Call ourselves recursively to do the stage 1 and then stage 2 * Call ourselves recursively to do the stage 1 and then stage 2
* translations. * translations if mmu_idx is a two-stage regime.
*/ */
if (arm_feature(env, ARM_FEATURE_EL2)) { if (arm_feature(env, ARM_FEATURE_EL2)) {
hwaddr ipa; hwaddr ipa;
@ -11893,9 +11893,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
int ret; int ret;
ARMCacheAttrs cacheattrs2 = {0}; ARMCacheAttrs cacheattrs2 = {0};
ret = get_phys_addr(env, address, access_type, ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
stage_1_mmu_idx(mmu_idx), &ipa, attrs, attrs, prot, page_size, fi, cacheattrs);
prot, page_size, fi, cacheattrs);
/* If S1 fails or S2 is disabled, return early. */ /* If S1 fails or S2 is disabled, return early. */
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) { if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {