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tcg: Introduce helpers for integer min/max

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These operations are re-invented by several targets so far.
Several supported hosts have insns for these, so place the
expanders out-of-line for a future introduction of tcg opcodes.

Backports commit b87fb8cd9f9a0ba599ff79e7bf03222da02e5724 from qemu
This commit is contained in:
Richard Henderson 2018-05-14 07:29:35 -04:00 committed by Lioncash
parent b22f822858
commit eef66443b2
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
16 changed files with 169 additions and 0 deletions
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8
qemu/aarch64.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64
#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64
#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64 #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64
#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64
#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64
#define tcg_gen_smin_i32 tcg_gen_smin_i32_aarch64
#define tcg_gen_smin_i64 tcg_gen_smin_i64_aarch64
#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64 #define tcg_gen_st_i32 tcg_gen_st_i32_aarch64
#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64 #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64
#define tcg_gen_st_vec tcg_gen_st_vec_aarch64 #define tcg_gen_st_vec tcg_gen_st_vec_aarch64
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64 #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
#define tcg_gen_umax_i32 tcg_gen_umax_i32_aarch64
#define tcg_gen_umax_i64 tcg_gen_umax_i64_aarch64
#define tcg_gen_umin_i32 tcg_gen_umin_i32_aarch64
#define tcg_gen_umin_i64 tcg_gen_umin_i64_aarch64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64

8
qemu/aarch64eb.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb
#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb
#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb
#define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64eb
#define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64eb
#define tcg_gen_smin_i32 tcg_gen_smin_i32_aarch64eb
#define tcg_gen_smin_i64 tcg_gen_smin_i64_aarch64eb
#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb #define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb
#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb #define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb
#define tcg_gen_st_vec tcg_gen_st_vec_aarch64eb #define tcg_gen_st_vec tcg_gen_st_vec_aarch64eb
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb #define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb #define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
#define tcg_gen_umax_i32 tcg_gen_umax_i32_aarch64eb
#define tcg_gen_umax_i64 tcg_gen_umax_i64_aarch64eb
#define tcg_gen_umin_i32 tcg_gen_umin_i32_aarch64eb
#define tcg_gen_umin_i64 tcg_gen_umin_i64_aarch64eb
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64eb #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_aarch64eb
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64eb #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_aarch64eb
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64eb #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_aarch64eb

8
qemu/arm.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_arm #define tcg_gen_shri_i32 tcg_gen_shri_i32_arm
#define tcg_gen_shri_i64 tcg_gen_shri_i64_arm #define tcg_gen_shri_i64 tcg_gen_shri_i64_arm
#define tcg_gen_shri_vec tcg_gen_shri_vec_arm #define tcg_gen_shri_vec tcg_gen_shri_vec_arm
#define tcg_gen_smax_i32 tcg_gen_smax_i32_arm
#define tcg_gen_smax_i64 tcg_gen_smax_i64_arm
#define tcg_gen_smin_i32 tcg_gen_smin_i32_arm
#define tcg_gen_smin_i64 tcg_gen_smin_i64_arm
#define tcg_gen_st_i32 tcg_gen_st_i32_arm #define tcg_gen_st_i32 tcg_gen_st_i32_arm
#define tcg_gen_st_i64 tcg_gen_st_i64_arm #define tcg_gen_st_i64 tcg_gen_st_i64_arm
#define tcg_gen_st_vec tcg_gen_st_vec_arm #define tcg_gen_st_vec tcg_gen_st_vec_arm
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm
#define tcg_gen_subi_i32 tcg_gen_subi_i32_arm #define tcg_gen_subi_i32 tcg_gen_subi_i32_arm
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm #define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
#define tcg_gen_umax_i32 tcg_gen_umax_i32_arm
#define tcg_gen_umax_i64 tcg_gen_umax_i64_arm
#define tcg_gen_umin_i32 tcg_gen_umin_i32_arm
#define tcg_gen_umin_i64 tcg_gen_umin_i64_arm
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_arm #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_arm
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_arm #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_arm
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_arm #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_arm

8
qemu/armeb.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb #define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb
#define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb #define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb
#define tcg_gen_shri_vec tcg_gen_shri_vec_armeb #define tcg_gen_shri_vec tcg_gen_shri_vec_armeb
#define tcg_gen_smax_i32 tcg_gen_smax_i32_armeb
#define tcg_gen_smax_i64 tcg_gen_smax_i64_armeb
#define tcg_gen_smin_i32 tcg_gen_smin_i32_armeb
#define tcg_gen_smin_i64 tcg_gen_smin_i64_armeb
#define tcg_gen_st_i32 tcg_gen_st_i32_armeb #define tcg_gen_st_i32 tcg_gen_st_i32_armeb
#define tcg_gen_st_i64 tcg_gen_st_i64_armeb #define tcg_gen_st_i64 tcg_gen_st_i64_armeb
#define tcg_gen_st_vec tcg_gen_st_vec_armeb #define tcg_gen_st_vec tcg_gen_st_vec_armeb
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb #define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb #define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
#define tcg_gen_umax_i32 tcg_gen_umax_i32_armeb
#define tcg_gen_umax_i64 tcg_gen_umax_i64_armeb
#define tcg_gen_umin_i32 tcg_gen_umin_i32_armeb
#define tcg_gen_umin_i64 tcg_gen_umin_i64_armeb
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_armeb #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_armeb
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_armeb #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_armeb
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_armeb #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_armeb

8
qemu/header_gen.py
View file

@ -2766,6 +2766,10 @@ symbols = (
'tcg_gen_shri_i32', 'tcg_gen_shri_i32',
'tcg_gen_shri_i64', 'tcg_gen_shri_i64',
'tcg_gen_shri_vec', 'tcg_gen_shri_vec',
'tcg_gen_smax_i32',
'tcg_gen_smax_i64',
'tcg_gen_smin_i32',
'tcg_gen_smin_i64',
'tcg_gen_st_i32', 'tcg_gen_st_i32',
'tcg_gen_st_i64', 'tcg_gen_st_i64',
'tcg_gen_st_vec', 'tcg_gen_st_vec',
@ -2779,6 +2783,10 @@ symbols = (
'tcg_gen_subfi_i64', 'tcg_gen_subfi_i64',
'tcg_gen_subi_i32', 'tcg_gen_subi_i32',
'tcg_gen_subi_i64', 'tcg_gen_subi_i64',
'tcg_gen_umax_i32',
'tcg_gen_umax_i64',
'tcg_gen_umin_i32',
'tcg_gen_umin_i64',
'tcg_gen_vec_add8_i64', 'tcg_gen_vec_add8_i64',
'tcg_gen_vec_add16_i64', 'tcg_gen_vec_add16_i64',
'tcg_gen_vec_add32_i64', 'tcg_gen_vec_add32_i64',

8
qemu/m68k.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k #define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k
#define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k #define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k
#define tcg_gen_shri_vec tcg_gen_shri_vec_m68k #define tcg_gen_shri_vec tcg_gen_shri_vec_m68k
#define tcg_gen_smax_i32 tcg_gen_smax_i32_m68k
#define tcg_gen_smax_i64 tcg_gen_smax_i64_m68k
#define tcg_gen_smin_i32 tcg_gen_smin_i32_m68k
#define tcg_gen_smin_i64 tcg_gen_smin_i64_m68k
#define tcg_gen_st_i32 tcg_gen_st_i32_m68k #define tcg_gen_st_i32 tcg_gen_st_i32_m68k
#define tcg_gen_st_i64 tcg_gen_st_i64_m68k #define tcg_gen_st_i64 tcg_gen_st_i64_m68k
#define tcg_gen_st_vec tcg_gen_st_vec_m68k #define tcg_gen_st_vec tcg_gen_st_vec_m68k
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k
#define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k #define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k #define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
#define tcg_gen_umax_i32 tcg_gen_umax_i32_m68k
#define tcg_gen_umax_i64 tcg_gen_umax_i64_m68k
#define tcg_gen_umin_i32 tcg_gen_umin_i32_m68k
#define tcg_gen_umin_i64 tcg_gen_umin_i64_m68k
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_m68k #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_m68k
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_m68k #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_m68k
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_m68k #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_m68k

8
qemu/mips.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips #define tcg_gen_shri_vec tcg_gen_shri_vec_mips
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips
#define tcg_gen_st_i32 tcg_gen_st_i32_mips #define tcg_gen_st_i32 tcg_gen_st_i32_mips
#define tcg_gen_st_i64 tcg_gen_st_i64_mips #define tcg_gen_st_i64 tcg_gen_st_i64_mips
#define tcg_gen_st_vec tcg_gen_st_vec_mips #define tcg_gen_st_vec tcg_gen_st_vec_mips
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips #define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips

8
qemu/mips64.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64 #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips64
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips64
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64 #define tcg_gen_st_i32 tcg_gen_st_i32_mips64
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64 #define tcg_gen_st_i64 tcg_gen_st_i64_mips64
#define tcg_gen_st_vec tcg_gen_st_vec_mips64 #define tcg_gen_st_vec tcg_gen_st_vec_mips64
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64 #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips64
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips64
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips64
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64

8
qemu/mips64el.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64el
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64el
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mips64el
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mips64el
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64el #define tcg_gen_st_i32 tcg_gen_st_i32_mips64el
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64el #define tcg_gen_st_i64 tcg_gen_st_i64_mips64el
#define tcg_gen_st_vec tcg_gen_st_vec_mips64el #define tcg_gen_st_vec tcg_gen_st_vec_mips64el
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el #define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el #define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mips64el
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mips64el
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mips64el
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mips64el
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64el #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mips64el
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64el #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mips64el
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64el #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mips64el

8
qemu/mipsel.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel #define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel #define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel
#define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel #define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel
#define tcg_gen_smax_i32 tcg_gen_smax_i32_mipsel
#define tcg_gen_smax_i64 tcg_gen_smax_i64_mipsel
#define tcg_gen_smin_i32 tcg_gen_smin_i32_mipsel
#define tcg_gen_smin_i64 tcg_gen_smin_i64_mipsel
#define tcg_gen_st_i32 tcg_gen_st_i32_mipsel #define tcg_gen_st_i32 tcg_gen_st_i32_mipsel
#define tcg_gen_st_i64 tcg_gen_st_i64_mipsel #define tcg_gen_st_i64 tcg_gen_st_i64_mipsel
#define tcg_gen_st_vec tcg_gen_st_vec_mipsel #define tcg_gen_st_vec tcg_gen_st_vec_mipsel
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel #define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel #define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
#define tcg_gen_umax_i32 tcg_gen_umax_i32_mipsel
#define tcg_gen_umax_i64 tcg_gen_umax_i64_mipsel
#define tcg_gen_umin_i32 tcg_gen_umin_i32_mipsel
#define tcg_gen_umin_i64 tcg_gen_umin_i64_mipsel
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mipsel #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_mipsel
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mipsel #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_mipsel
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mipsel #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_mipsel

8
qemu/powerpc.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc #define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc
#define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc #define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc
#define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc #define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc
#define tcg_gen_smax_i32 tcg_gen_smax_i32_powerpc
#define tcg_gen_smax_i64 tcg_gen_smax_i64_powerpc
#define tcg_gen_smin_i32 tcg_gen_smin_i32_powerpc
#define tcg_gen_smin_i64 tcg_gen_smin_i64_powerpc
#define tcg_gen_st_i32 tcg_gen_st_i32_powerpc #define tcg_gen_st_i32 tcg_gen_st_i32_powerpc
#define tcg_gen_st_i64 tcg_gen_st_i64_powerpc #define tcg_gen_st_i64 tcg_gen_st_i64_powerpc
#define tcg_gen_st_vec tcg_gen_st_vec_powerpc #define tcg_gen_st_vec tcg_gen_st_vec_powerpc
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc #define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc #define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
#define tcg_gen_umax_i32 tcg_gen_umax_i32_powerpc
#define tcg_gen_umax_i64 tcg_gen_umax_i64_powerpc
#define tcg_gen_umin_i32 tcg_gen_umin_i32_powerpc
#define tcg_gen_umin_i64 tcg_gen_umin_i64_powerpc
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_powerpc #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_powerpc
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_powerpc #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_powerpc
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_powerpc #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_powerpc

8
qemu/sparc.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc
#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc
#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc
#define tcg_gen_smin_i32 tcg_gen_smin_i32_sparc
#define tcg_gen_smin_i64 tcg_gen_smin_i64_sparc
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc #define tcg_gen_st_i32 tcg_gen_st_i32_sparc
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc #define tcg_gen_st_i64 tcg_gen_st_i64_sparc
#define tcg_gen_st_vec tcg_gen_st_vec_sparc #define tcg_gen_st_vec tcg_gen_st_vec_sparc
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc #define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc #define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
#define tcg_gen_umax_i32 tcg_gen_umax_i32_sparc
#define tcg_gen_umax_i64 tcg_gen_umax_i64_sparc
#define tcg_gen_umin_i32 tcg_gen_umin_i32_sparc
#define tcg_gen_umin_i64 tcg_gen_umin_i64_sparc
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc

8
qemu/sparc64.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64 #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64
#define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc64
#define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc64
#define tcg_gen_smin_i32 tcg_gen_smin_i32_sparc64
#define tcg_gen_smin_i64 tcg_gen_smin_i64_sparc64
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc64 #define tcg_gen_st_i32 tcg_gen_st_i32_sparc64
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc64 #define tcg_gen_st_i64 tcg_gen_st_i64_sparc64
#define tcg_gen_st_vec tcg_gen_st_vec_sparc64 #define tcg_gen_st_vec tcg_gen_st_vec_sparc64
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64 #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
#define tcg_gen_umax_i32 tcg_gen_umax_i32_sparc64
#define tcg_gen_umax_i64 tcg_gen_umax_i64_sparc64
#define tcg_gen_umin_i32 tcg_gen_umin_i32_sparc64
#define tcg_gen_umin_i64 tcg_gen_umin_i64_sparc64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_sparc64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_sparc64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_sparc64

40
qemu/tcg/tcg-op.c
View file

@ -1040,6 +1040,26 @@ void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg)
} }
} }
void tcg_gen_smin_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_movcond_i32(s, TCG_COND_LT, ret, a, b, a, b);
}
void tcg_gen_umin_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_movcond_i32(s, TCG_COND_LTU, ret, a, b, a, b);
}
void tcg_gen_smax_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_movcond_i32(s, TCG_COND_LT, ret, a, b, b, a);
}
void tcg_gen_umax_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_movcond_i32(s, TCG_COND_LTU, ret, a, b, b, a);
}
/* 64-bit ops */ /* 64-bit ops */
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
@ -2452,6 +2472,26 @@ void tcg_gen_mulsu2_i64(TCGContext *s, TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1,
tcg_temp_free_i64(s, t2); tcg_temp_free_i64(s, t2);
} }
void tcg_gen_smin_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_movcond_i64(s, TCG_COND_LT, ret, a, b, a, b);
}
void tcg_gen_umin_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_movcond_i64(s, TCG_COND_LTU, ret, a, b, a, b);
}
void tcg_gen_smax_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_movcond_i64(s, TCG_COND_LT, ret, a, b, b, a);
}
void tcg_gen_umax_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_movcond_i64(s, TCG_COND_LTU, ret, a, b, b, a);
}
/* Size changing operations. */ /* Size changing operations. */
void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg) void tcg_gen_extrl_i64_i32(TCGContext *s, TCGv_i32 ret, TCGv_i64 arg)

17
qemu/tcg/tcg-op.h
View file

@ -337,6 +337,10 @@ void tcg_gen_ext8u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_ext16u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_bswap16_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap16_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap32_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_smin_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_smax_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_umin_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_umax_i32(TCGContext *s, TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
static inline void tcg_gen_discard_i32(TCGContext *s, TCGv_i32 arg) static inline void tcg_gen_discard_i32(TCGContext *s, TCGv_i32 arg)
{ {
@ -522,6 +526,11 @@ void tcg_gen_ext32u_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap16_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap32_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap64_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_smin_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_smax_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umin_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umax_i64(TCGContext *s, TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
static inline void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg) static inline void tcg_gen_discard_i64(TCGContext *s, TCGv_i64 arg)
@ -1033,6 +1042,10 @@ void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCG
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
#define tcg_gen_muls2_tl tcg_gen_muls2_i64 #define tcg_gen_muls2_tl tcg_gen_muls2_i64
#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
#define tcg_gen_smin_tl tcg_gen_smin_i64
#define tcg_gen_umin_tl tcg_gen_umin_i64
#define tcg_gen_smax_tl tcg_gen_smax_i64
#define tcg_gen_umax_tl tcg_gen_umax_i64
#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
@ -1131,6 +1144,10 @@ void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCG
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
#define tcg_gen_muls2_tl tcg_gen_muls2_i32 #define tcg_gen_muls2_tl tcg_gen_muls2_i32
#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
#define tcg_gen_smin_tl tcg_gen_smin_i32
#define tcg_gen_umin_tl tcg_gen_umin_i32
#define tcg_gen_smax_tl tcg_gen_smax_i32
#define tcg_gen_umax_tl tcg_gen_umax_i32
#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32

8
qemu/x86_64.h
View file

@ -2760,6 +2760,10 @@
#define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64
#define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64
#define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64 #define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64
#define tcg_gen_smax_i32 tcg_gen_smax_i32_x86_64
#define tcg_gen_smax_i64 tcg_gen_smax_i64_x86_64
#define tcg_gen_smin_i32 tcg_gen_smin_i32_x86_64
#define tcg_gen_smin_i64 tcg_gen_smin_i64_x86_64
#define tcg_gen_st_i32 tcg_gen_st_i32_x86_64 #define tcg_gen_st_i32 tcg_gen_st_i32_x86_64
#define tcg_gen_st_i64 tcg_gen_st_i64_x86_64 #define tcg_gen_st_i64 tcg_gen_st_i64_x86_64
#define tcg_gen_st_vec tcg_gen_st_vec_x86_64 #define tcg_gen_st_vec tcg_gen_st_vec_x86_64
@ -2773,6 +2777,10 @@
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64 #define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64 #define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64 #define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
#define tcg_gen_umax_i32 tcg_gen_umax_i32_x86_64
#define tcg_gen_umax_i64 tcg_gen_umax_i64_x86_64
#define tcg_gen_umin_i32 tcg_gen_umin_i32_x86_64
#define tcg_gen_umin_i64 tcg_gen_umin_i64_x86_64
#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_x86_64 #define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_x86_64
#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_x86_64 #define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_x86_64
#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_x86_64 #define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_x86_64