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target/arm: Convert Neon VHADD 3-reg-same insns

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Convert the Neon VHADD insns in the 3-reg-same group to decodetree.

Backports commit cb294bca866f1cd776e44e03e5e432942bc676e8 from qemu
This commit is contained in:
Peter Maydell 2020-05-15 22:42:59 -04:00 committed by Lioncash
parent 4098e0b80a
commit f1028fe4a7
3 changed files with 28 additions and 3 deletions
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2
qemu/target/arm/neon-dp.decode
View file

@ -42,6 +42,8 @@
@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same

25
qemu/target/arm/translate-neon.inc.c
View file

@ -866,3 +866,28 @@ DO_3SAME_64_ENV(VQSHL_S64, gen_helper_neon_qshl_s64)
DO_3SAME_64_ENV(VQSHL_U64, gen_helper_neon_qshl_u64)
DO_3SAME_64_ENV(VQRSHL_S64, gen_helper_neon_qrshl_s64)
DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
#define DO_3SAME_32(INSN, FUNC) \
static void gen_##INSN##_3s(TCGContext *s, unsigned vece, uint32_t rd_ofs, \
uint32_t rn_ofs, uint32_t rm_ofs, \
uint32_t oprsz, uint32_t maxsz) \
{ \
static const GVecGen3 ops[4] = { \
{ .fni4 = gen_helper_neon_##FUNC##8 }, \
{ .fni4 = gen_helper_neon_##FUNC##16 }, \
{ .fni4 = gen_helper_neon_##FUNC##32 }, \
{ 0 }, \
}; \
tcg_gen_gvec_3(s, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece]); \
} \
static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
{ \
if (a->size > 2) { \
return false; \
} \
return do_3same(s, a, gen_##INSN##_3s); \
}
DO_3SAME_32(VHADD_S, hadd_s)
DO_3SAME_32(VHADD_U, hadd_u)

4
qemu/target/arm/translate.c
View file

@ -5581,6 +5581,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VML:
case NEON_3R_VSHL:
case NEON_3R_SHA:
case NEON_3R_VHADD:
/* Already handled by decodetree */
return 1;
}
@ -5661,9 +5662,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(s, rm, pass);
}
switch (op) {
case NEON_3R_VHADD:
GEN_NEON_INTEGER_OP(hadd);
break;
case NEON_3R_VRHADD:
GEN_NEON_INTEGER_OP(rhadd);
break;