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target-arm: implement IRQ/FIQ routing to Monitor mode
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Backports commit de38d23b542efca54108ef28bcc0efe96f378d2e from qemu
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4d9c9f893e
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@ -3743,6 +3743,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
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/* Disable IRQ and imprecise data aborts. */
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mask = CPSR_A | CPSR_I;
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offset = 4;
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if (env->cp15.scr_el3 & SCR_IRQ) {
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/* IRQ routed to monitor mode */
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new_mode = ARM_CPU_MODE_MON;
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mask |= CPSR_F;
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}
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break;
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case EXCP_FIQ:
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new_mode = ARM_CPU_MODE_FIQ;
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@ -3750,6 +3755,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
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/* Disable FIQ, IRQ and imprecise data aborts. */
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mask = CPSR_A | CPSR_I | CPSR_F;
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offset = 4;
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if (env->cp15.scr_el3 & SCR_FIQ) {
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/* FIQ routed to monitor mode */
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new_mode = ARM_CPU_MODE_MON;
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}
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break;
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case EXCP_SMC:
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new_mode = ARM_CPU_MODE_MON;
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