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target-arm: implement IRQ/FIQ routing to Monitor mode

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SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.

Backports commit de38d23b542efca54108ef28bcc0efe96f378d2e from qemu
This commit is contained in:
Fabian Aggeler 2018-02-11 18:50:51 -05:00 committed by Lioncash
parent 4d9c9f893e
commit f120ad5308
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 9 additions and 0 deletions
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9
qemu/target-arm/helper.c
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@ -3743,6 +3743,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
if (env->cp15.scr_el3 & SCR_IRQ) {
/* IRQ routed to monitor mode */
new_mode = ARM_CPU_MODE_MON;
mask |= CPSR_F;
}
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
@ -3750,6 +3755,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 4;
if (env->cp15.scr_el3 & SCR_FIQ) {
/* FIQ routed to monitor mode */
new_mode = ARM_CPU_MODE_MON;
}
break;
case EXCP_SMC:
new_mode = ARM_CPU_MODE_MON;