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target-mips: add 24KEc CPU definition

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Define a new CPU definition supporting 24KEc cores, similar to
the existing 24Kc, but with added support for DSP instructions
and MIPS16e (and without FPU).

Backports commit e9deaad8a58c899dc32e9fdeff9e533070e79dca from qemu
This commit is contained in:
André Draszik 2018-02-26 03:50:16 -05:00 committed by Lioncash
parent e24890a580
commit f14ece4aa1
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 38 additions and 0 deletions
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38
qemu/target-mips/translate_init.c
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@ -334,6 +334,44 @@ static const mips_def_t mips_defs[] =
CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_R4000,
},
{
"24KEc",
0x00019600,
MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
MIPS_CONFIG2,
MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
0,0,
0,0,
0,
0,
0,
4,
32,
2,
/* we have a DSP, but no FPU */
0x1378FF1F,
0,
0,
0,
0,
0,
0,
32,
32,
0,0,
0,0,
0,0,
0,0,
0,0,
0,0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
MMU_TYPE_R4000,
},
{
"24Kf",
0x00019300,