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target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline

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Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.

Backports commit 2aeba0d007d33efa12a6339bb140aa634e0d52eb from qemu
This commit is contained in:
Julia Suvorova 2018-06-29 14:15:31 -05:00 committed by Lioncash
parent 65d0e176c3
commit f28514178a
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 16 additions and 2 deletions
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18
qemu/target/arm/translate.c
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@ -1137,7 +1137,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, TCGMemOp opc) int index, TCGMemOp opc)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv addr = gen_aa32_addr(s, a32, opc); TCGv addr;
if (arm_dc_feature(s, ARM_FEATURE_M) &&
!arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
opc |= MO_ALIGN;
}
addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_ld_i32(s->uc, val, addr, index, opc); tcg_gen_qemu_ld_i32(s->uc, val, addr, index, opc);
tcg_temp_free(tcg_ctx, addr); tcg_temp_free(tcg_ctx, addr);
} }
@ -1146,7 +1153,14 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, TCGMemOp opc) int index, TCGMemOp opc)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
TCGv addr = gen_aa32_addr(s, a32, opc); TCGv addr;
if (arm_dc_feature(s, ARM_FEATURE_M) &&
!arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
opc |= MO_ALIGN;
}
addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_st_i32(s->uc, val, addr, index, opc); tcg_gen_qemu_st_i32(s->uc, val, addr, index, opc);
tcg_temp_free(tcg_ctx, addr); tcg_temp_free(tcg_ctx, addr);
} }