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target/mips: Update gen_flt_ldst()

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Update gen_flt_ldst() in order to reuse the functions for nanoMIPS

Backports commit b52d3bfa2d54d99ef25f6d008815eecc53b67bfe from qemu
This commit is contained in:
Yongbok Kim 2018-07-03 00:59:44 -04:00 committed by Lioncash
parent a246bdb5b3
commit f2d68a4079
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 7 deletions
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15
qemu/target/mips/translate.c
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@ -2449,12 +2449,10 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
/* Load and store */
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
int base, int16_t offset)
TCGv t0)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_base_offset_addr(ctx, t0, base, offset);
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
@ -2497,15 +2495,16 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
default:
MIPS_INVAL("flt_ldst");
generate_exception_end(ctx, EXCP_RI);
goto out;
break;
}
out:
tcg_temp_free(tcg_ctx, t0);
}
static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
int rs, int16_t imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
switch (op) {
@ -2514,11 +2513,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
check_insn(ctx, ISA_MIPS2);
/* Fallthrough */
default:
gen_flt_ldst(ctx, op, rt, rs, imm);
gen_base_offset_addr(ctx, t0, rs, imm);
gen_flt_ldst(ctx, op, rt, t0);
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
tcg_temp_free(tcg_ctx, t0);
}
/* Arithmetic with immediate operand */