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target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3

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This is part of a reorganization to the set of mmu_idx.
The EL3 regime only has a single stage translation, and
is always secure.

Backports commit 127b2b086303296289099a6fb10bbc51077f1d53 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 14:38:41 -04:00 committed by Lioncash
parent 1a672fc3b1
commit f45ab0614e
4 changed files with 11 additions and 11 deletions
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4
qemu/target/arm/cpu.h
View file

@ -2803,7 +2803,7 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A,
ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
@ -2829,7 +2829,7 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_E10_0 = 1 << 0,
ARMMMUIdxBit_E10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_S1E3 = 1 << 3,
ARMMMUIdxBit_SE3 = 1 << 3,
ARMMMUIdxBit_SE10_0 = 1 << 4,
ARMMMUIdxBit_SE10_1 = 1 << 5,
ARMMMUIdxBit_Stage2 = 1 << 6,

14
qemu/target/arm/helper.c
View file

@ -2963,7 +2963,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* stage 1 current state PL1: ATS1CPR, ATS1CPW */
switch (el) {
case 3:
mmu_idx = ARMMMUIdx_S1E3;
mmu_idx = ARMMMUIdx_SE3;
break;
case 2:
mmu_idx = ARMMMUIdx_Stage1_E1;
@ -3045,7 +3045,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
mmu_idx = ARMMMUIdx_S1E2;
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx = ARMMMUIdx_S1E3;
mmu_idx = ARMMMUIdx_SE3;
break;
default:
g_assert_not_reached();
@ -3794,7 +3794,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E3);
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
}
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -3827,7 +3827,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
#if 0
CPUState *cs = env_cpu(env);
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E3);
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
#endif
}
@ -3856,7 +3856,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E3);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
}
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -3914,7 +3914,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
ARMMMUIdxBit_S1E3);
ARMMMUIdxBit_SE3);
#endif
}
@ -8554,7 +8554,7 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_Stage2:
case ARMMMUIdx_S1E2:
return 2;
case ARMMMUIdx_S1E3:
case ARMMMUIdx_SE3:
return 3;
case ARMMMUIdx_SE10_0:
return arm_el_is_aa64(env, 3) ? 1 : 3;

2
qemu/target/arm/internals.h
View file

@ -821,7 +821,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_MPriv:
case ARMMMUIdx_MUser:
return false;
case ARMMMUIdx_S1E3:
case ARMMMUIdx_SE3:
case ARMMMUIdx_SE10_0:
case ARMMMUIdx_SE10_1:
case ARMMMUIdx_MSPrivNegPri:

2
qemu/target/arm/translate.c
View file

@ -150,7 +150,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
case ARMMMUIdx_S1E3:
case ARMMMUIdx_SE3:
case ARMMMUIdx_SE10_0:
case ARMMMUIdx_SE10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);