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target/arm: Make MPU_CTRL register banked for v8M

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Make the MPU_CTRL register banked if v8M security extensions are
enabled.

Backports commit ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9 from qemu
This commit is contained in:
Peter Maydell 2018-03-04 21:08:13 -05:00 committed by Lioncash
parent 683830d5ac
commit f88f4b5e31
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 4 additions and 3 deletions
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2
qemu/target/arm/cpu.h
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@ -434,7 +434,7 @@ typedef struct CPUARMState {
uint32_t dfsr; /* Debug Fault Status Register */ uint32_t dfsr; /* Debug Fault Status Register */
uint32_t mmfar; /* MemManage Fault Address */ uint32_t mmfar; /* MemManage Fault Address */
uint32_t bfar; /* BusFault Address */ uint32_t bfar; /* BusFault Address */
unsigned mpu_ctrl; /* MPU_CTRL */ unsigned mpu_ctrl[2]; /* MPU_CTRL */
int exception; int exception;
uint32_t primask[2]; uint32_t primask[2];
uint32_t faultmask[2]; uint32_t faultmask[2];

5
qemu/target/arm/helper.c
View file

@ -6365,7 +6365,7 @@ static inline bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx) ARMMMUIdx mmu_idx)
{ {
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
switch (env->v7m.mpu_ctrl & switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
case R_V7M_MPU_CTRL_ENABLE_MASK: case R_V7M_MPU_CTRL_ENABLE_MASK:
/* Enabled, but not for HardFault and NMI */ /* Enabled, but not for HardFault and NMI */
@ -7521,7 +7521,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu,
} }
if (arm_feature(env, ARM_FEATURE_M)) { if (arm_feature(env, ARM_FEATURE_M)) {
return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]
& R_V7M_MPU_CTRL_PRIVDEFENA_MASK;
} else { } else {
return regime_sctlr(env, mmu_idx) & SCTLR_BR; return regime_sctlr(env, mmu_idx) & SCTLR_BR;
} }