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target-i386: Move APIC ID compatibility code to pc.c

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The APIC ID compatibility code is required only for PC, and now that
x86_cpu_initfn() doesn't use x86_cpu_apic_id_from_index() anymore, that
code can be moved to pc.c.

Backports commit de13197a38cf45c990802661a057f64a05426cbc from qemu
This commit is contained in:
Eduardo Habkost 2018-02-12 15:52:10 -05:00 committed by Lioncash
parent a55484021b
commit fc39930347
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 33 additions and 32 deletions
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33
qemu/hw/i386/pc.c
View file

@ -25,7 +25,9 @@
#include "hw/hw.h" #include "hw/hw.h"
#include "hw/i386/pc.h" #include "hw/i386/pc.h"
#include "sysemu/cpus.h"
#include "sysemu/sysemu.h" #include "sysemu/sysemu.h"
#include "target-i386/topology.h"
#include "qapi-visit.h" #include "qapi-visit.h"
@ -179,3 +181,34 @@ void pc_machine_register_types(struct uc_struct *uc)
{ {
type_register_static(uc, &pc_machine_info); type_register_static(uc, &pc_machine_info);
} }
/* Enables contiguous-apic-ID mode, for compatibility */
static bool compat_apic_id_mode;
void enable_compat_apic_id_mode(void)
{
compat_apic_id_mode = true;
}
/* Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
* alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
* no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
* all CPUs up to max_cpus.
*/
uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
{
uint32_t correct_id;
correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
if (compat_apic_id_mode) {
if (cpu_index != correct_id) {
//error_report("APIC IDs set in compatibility mode, "
// "CPU topology won't match the configuration");
}
return cpu_index;
} else {
return correct_id;
}
}

32
qemu/target-i386/cpu.c
View file

@ -23,7 +23,6 @@
#include "cpu.h" #include "cpu.h"
#include "sysemu/cpus.h" #include "sysemu/cpus.h"
#include "topology.h"
#include "qapi/qmp/qerror.h" #include "qapi/qmp/qerror.h"
@ -2432,37 +2431,6 @@ out:
return 0; return 0;
} }
/* Enables contiguous-apic-ID mode, for compatibility */
static bool compat_apic_id_mode;
void enable_compat_apic_id_mode(void)
{
compat_apic_id_mode = true;
}
/* Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
* alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
* no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
* all CPUs up to max_cpus.
*/
uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
{
uint32_t correct_id;
correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
if (compat_apic_id_mode) {
if (cpu_index != correct_id) {
//error_report("APIC IDs set in compatibility mode, "
// "CPU topology won't match the configuration");
}
return cpu_index;
} else {
return correct_id;
}
}
static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque) static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{ {
//printf("... X86 initialize (object)\n"); //printf("... X86 initialize (object)\n");