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target/arm: Enable FP16 in '-cpu max'

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Set the MVFR1 ID register FPHP and SIMDHP fields to indicate
that our "-cpu max" has v8.2-FP16.

Backports commit 5f07817eb94542e39a419baafa3026b15e8d33f7
This commit is contained in:
Peter Maydell 2021-03-01 18:00:10 -05:00 committed by Lioncash
parent b948636c4a
commit ff74ede2fd
2 changed files with 7 additions and 8 deletions
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3
qemu/target/arm/cpu.c
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@ -1949,7 +1949,8 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->isar.id_isar6 = t; cpu->isar.id_isar6 = t;
t = cpu->isar.mvfr1; t = cpu->isar.mvfr1;
t = FIELD_DP32(t, MVFR1, FPHP, 2); /* v8.0 FP support */ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
cpu->isar.mvfr1 = t; cpu->isar.mvfr1 = t;
t = cpu->isar.mvfr2; t = cpu->isar.mvfr2;

12
qemu/target/arm/cpu64.c
View file

@ -356,13 +356,11 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
cpu->isar.id_dfr0 = u; cpu->isar.id_dfr0 = u;
// Unicorn: we lie and enable them anyway u = cpu->isar.mvfr1;
/* u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
* so do not set MVFR1.FPHP. Strictly speaking this is not legal, cpu->isar.mvfr1 = u;
* but it is also not legal to enable SVE without support for FP16,
* and enabling SVE in system mode is more useful in the short term.
*/
/* For usermode -cpu max we can use a larger and more efficient DCZ /* For usermode -cpu max we can use a larger and more efficient DCZ
* blocksize since we don't have to follow what the hardware does. * blocksize since we don't have to follow what the hardware does.
*/ */