7 commits

Author	SHA1	Message	Date
Maciej W. Rozycki	15bfd1dde7	target-mips: Tighten ISA level checks ... Tighten ISA level checks down to MIPS II that many of our instructions are missing. Also make sure any 64-bit instruction enables are only applied to 64-bit processors, that is ones that implement at least the MIPS III ISA. Backports commit d9224450208e0de62323b64ace91f98bc31d6e2c from qemu	2018-02-11 16:37:17 -05:00
Richard Henderson	dafc44c0a5	target-mips: Use CPU_LOG_INT for logging related to interrupts ... There are now no unconditional uses of qemu_log in the subdirectory. Backports commit c85570163bdf1ba29cb52a63f22ff1c48f1b9398 from qemu	2018-02-10 21:12:41 -05:00
xorstream	69ae8f7987	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
xorstream	72a497bc14	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
xorstream	fac6a66860	platform.h move #3	2017-01-21 00:13:21 +11:00
xorstream	1aeaf5c40d	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh	344d016104	import	2015-08-21 15:04:50 +08:00