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  • 2246f787e2
         Merge pull request #30 from merryhime/aarch64-host master Mai M 2022-02-15 18:12:01 -0500
  • cb5bf64515 Fix build on aarch64 Merry 2022-02-15 17:49:32 +0000
  • 2cf18d5aab Update version for v6.0.0-rc3 release Peter Maydell 2021-04-19 11:56:09 -0400
  • 00aebd3410 target/mips: Fix TCG temporary leak in gen_cache_operation() Philippe Mathieu-Daudé 2021-04-19 11:55:30 -0400
  • d248e38ec7 target/arm: Check PAGE_WRITE_ORG for MTE writeability Richard Henderson 2021-04-19 11:52:56 -0400
  • bbb163f2dc Update version for v6.0.0-rc2 release Peter Maydell 2021-04-19 11:51:53 -0400
  • 988bf2f458 target/i386: Verify memory operand for lcall and ljmp Richard Henderson 2021-04-01 16:03:57 -0400
  • 0a648854a8 Update version for v6.0.0-rc1 release Peter Maydell 2021-03-30 15:32:15 -0400
  • 82ce9221a0 target/arm: Make number of counters in PMCR follow the CPU Peter Maydell 2021-03-30 15:30:29 -0400
  • 289eed9550 Update version for v6.0.0-rc0 release Peter Maydell 2021-03-30 15:26:17 -0400
  • 250e263ae3 target/arm: Make M-profile VTOR loads on reset handle memory aliasing Peter Maydell 2021-03-30 15:24:15 -0400
  • 83116e69b5 target/riscv: Prevent lost illegal instruction exceptions Georg Kotheimer 2021-03-30 15:22:58 -0400
  • a1edab5abf target/riscv: Add proper two-stage lookup exception detection Georg Kotheimer 2021-03-30 15:19:22 -0400
  • d18b402732 target/riscv: Fix read and write accesses to vsip and vsie Georg Kotheimer 2021-03-30 15:16:09 -0400
  • e74588a57f target/riscv: Use background registers also for MSTATUS_MPV Georg Kotheimer 2021-03-30 15:14:11 -0400
  • a392976e77 target/riscv: Make VSTIP and VSEIP read-only in hip Georg Kotheimer 2021-03-30 15:13:18 -0400
  • eb778614fb target/riscv: Adjust privilege level for HLV(X)/HSV instructions Georg Kotheimer 2021-03-30 15:10:40 -0400
  • 85ccd1a71e target/riscv: flush TLB pages if PMP permission has been changed Jim Shu 2021-03-30 15:09:11 -0400
  • 7dad65cea1 target/riscv: add log of PMP permission checking Jim Shu 2021-03-30 15:07:49 -0400
  • d1ee86a6b2 target/riscv: propagate PMP permission to TLB page Jim Shu 2021-03-30 15:04:10 -0400
  • da652cb603 target/riscv: fix vs() to return proper error code Frank Chang 2021-03-30 14:59:30 -0400
  • 9153951f1e tcg: Fix prototypes for tcg_out_vec_op and tcg_out_op Miroslav Rezanina 2021-03-30 14:56:48 -0400
  • ebacc7febd target/arm: Update sve reduction vs simd_desc Richard Henderson 2021-03-30 14:44:52 -0400
  • 1b05fd82b7 target/arm: Update WHILE for PREDDESC Richard Henderson 2021-03-30 14:42:39 -0400
  • c374bdc9ca target/arm: Update CNTP for PREDDESC Richard Henderson 2021-03-30 14:40:59 -0400
  • 7e26827ea5 target/arm: Update BRKA, BRKB, BRKN for PREDDESC Richard Henderson 2021-03-30 14:37:59 -0400
  • 452891c530 target/arm: Update find_last_active for PREDDESC Richard Henderson 2021-03-30 14:33:28 -0400
  • e7cec52fac target/arm: Fix sve_punpk_p vs odd vector lengths Richard Henderson 2021-03-30 14:32:42 -0400
  • 78c016ef83 target/arm: Fix sve_zip_p vs odd vector lengths Richard Henderson 2021-03-30 14:29:31 -0400
  • 1aed8cee64 target/arm: Fix sve_uzp_p vs odd vector lengths Richard Henderson 2021-03-30 14:27:47 -0400
  • 9777741703 target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature Mark Cave-Ayland 2021-03-12 14:55:33 -0500
  • 7d5dfd6b53 m68k: add MSP detection support for stack pointer swap helpers Lucien Murray-Pitts 2021-03-12 14:53:45 -0500
  • f0846b7c34 m68k: MOVEC insn. should generate exception if wrong CR is accessed Lucien Murray-Pitts 2021-03-12 14:49:19 -0500
  • 0e992c16fd m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to m68k_move_to/from Lucien Murray-Pitts 2021-03-12 14:39:58 -0500
  • c6d5eea686 m68k: improve comments on m68k_move_to/from helpers Lucien Murray-Pitts 2021-03-12 14:38:47 -0500
  • 32e9e17576 m68k: improve cpu instantiation comments Lucien Murray-Pitts 2021-03-12 14:34:12 -0500
  • 8f391fe579 target/m68k: reformat m68k_features enum Mark Cave-Ayland 2021-03-12 14:31:22 -0500
  • 0be85bf91a target/m68k: don't set SSW ATC bit for physical bus errors Mark Cave-Ayland 2021-03-12 14:29:28 -0500
  • 945dd6fba9 target/m68k: implement rtr instruction Laurent Vivier 2021-03-12 14:28:21 -0500
  • c1ca2ae0ba include/exec: lightly re-arrange TranslationBlock Alex Bennée 2021-03-09 13:24:54 -0500
  • d83b1ea283 tcg: Split out tcg_raise_tb_overflow Richard Henderson 2021-03-09 13:23:01 -0500
  • 6ef897bbad tcg/aarch64: Fix generation of scalar vector operations Richard Henderson 2021-03-09 13:22:04 -0500
  • b01d5a9fdf tcg/aarch64: Fix I3617_CMLE0 Richard Henderson 2021-03-09 13:17:14 -0500
  • 043d65862a tcg/aarch64: Fix constant subtraction in tcg_out_addsub2 Richard Henderson 2021-03-09 13:16:27 -0500
  • e54d0916ef target/riscv/pmp: Raise exception if no PMP entry is configured Atish Patra 2021-03-08 15:39:46 -0500
  • 037b9e3bd1 target/riscv: csr: Remove compile time XLEN checks Alistair Francis 2021-03-08 15:34:28 -0500
  • 90abfa7c11 target/riscv: cpu_helper: Remove compile time XLEN checks Alistair Francis 2021-03-08 15:29:11 -0500
  • ea716ff2db target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis 2021-03-08 15:26:54 -0500
  • 5973588ac0 target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis 2021-03-08 15:22:33 -0500
  • b23e786779 riscv: spike: Remove target macro conditionals Alistair Francis 2021-03-08 15:20:39 -0500
  • 19c937f2cc target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis 2021-03-08 15:17:56 -0500
  • 8e4e0a6993 target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alex Richardson 2021-03-08 15:16:42 -0500
  • c50f8c9d93 target/riscv: Fix the bug of HLVX/HLV/HSV Yifei Jiang 2021-03-08 15:15:59 -0500
  • 416b2a0077 target/riscv: Split the Hypervisor execute load helpers Alistair Francis 2021-03-08 15:14:23 -0500
  • 4762dcda3c target/riscv: Remove the hyp load and store functions Alistair Francis 2021-03-08 15:11:09 -0500
  • bd81c057ed target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis 2021-03-08 15:03:13 -0500
  • e5a9b8fc17 target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis 2021-03-08 14:57:56 -0500
  • a998c18ad8 target/riscv: Add a virtualised MMU Mode Alistair Francis 2021-03-08 14:56:06 -0500
  • 757608b77c target/riscv/csr.c : add space before the open parenthesis '(' Xinhao Zhang 2021-03-08 14:53:54 -0500
  • 9d47840784 target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Yifei Jiang 2021-03-08 14:52:41 -0500
  • 281d851303 target/riscv: raise exception to HS-mode at get_physical_address Yifei Jiang 2021-03-08 14:42:50 -0500
  • d2cea344f0 target/riscv: Fix implementation of HLVX.WU instruction Georg Kotheimer 2021-03-08 14:40:27 -0500
  • 7351f09919 target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt Georg Kotheimer 2021-03-08 14:39:29 -0500
  • 640a26bf58 target/riscv: Fix update of hstatus.SPVP Georg Kotheimer 2021-03-08 14:38:14 -0500
  • 4805f204d8 riscv: Convert interrupt logs to use qemu_log_mask() Alistair Francis 2021-03-08 14:36:54 -0500
  • 320b59ddb9 qemu/atomic.h: rename atomic_ to qatomic_ Stefan Hajnoczi 2021-03-08 14:34:24 -0500
  • 1341de97f0 hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng 2021-03-08 14:01:56 -0500
  • d508a74a74 target/riscv: cpu: Add a new 'resetvec' property Bin Meng 2021-03-08 13:57:49 -0500
  • 0e14547c7d target/riscv: Support the Virtual Instruction fault Alistair Francis 2021-03-08 13:54:58 -0500
  • c3d9e15f02 target/riscv: Return the exception from invalid CSR accesses Alistair Francis 2021-03-08 13:49:06 -0500
  • dd9f854edb target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis 2021-03-08 13:35:59 -0500
  • 8e3d241d2c target/riscv: Only support little endian guests Alistair Francis 2021-03-08 13:34:20 -0500
  • 12d33edea5 target/riscv: Only support a single VSXL length Alistair Francis 2021-03-08 13:33:37 -0500
  • 1551a961ba target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis 2021-03-08 13:33:01 -0500
  • bf52a9b17e target/riscv: Update the Hypervisor trap return/entry Alistair Francis 2021-03-08 13:31:01 -0500
  • db749a279d target/riscv: Fix the interrupt cause code Alistair Francis 2021-03-08 13:28:09 -0500
  • a5311a267d target/riscv: Convert MSTATUS MTL to GVA Alistair Francis 2021-03-08 13:26:29 -0500
  • 7ceb984b60 target/riscv: Don't allow guest to write to htinst Alistair Francis 2021-03-08 13:22:46 -0500
  • 4972437f93 target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis 2021-03-08 12:58:58 -0500
  • a8bce9af7a target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis 2021-03-08 12:49:08 -0500
  • 9792907bcf target/riscv: Change the TLB page size depends on PMP entries. Zong Li 2021-03-08 12:46:16 -0500
  • 2edba8fcfe target/riscv: Fix the translation of physical address Zong Li 2021-03-08 12:43:33 -0500
  • 55be7adad9 riscv: Fix bug in setting pmpcfg CSR for RISCV64 Hou Weiying 2021-03-08 12:42:01 -0500
  • cde007ccb6 target/riscv: check before allocating TCG temps LIU Zhiwei 2021-03-08 12:41:17 -0500
  • 8fe29be764 target/riscv: Clean up fmv.w.x LIU Zhiwei 2021-03-08 12:39:28 -0500
  • 3af34d3df4 target/riscv: Check nanboxed inputs in trans_rvf.inc.c Richard Henderson 2021-03-08 12:37:08 -0500
  • ce54dfb4f7 target/riscv: Check nanboxed inputs to fp helpers Richard Henderson 2021-03-08 12:31:16 -0500
  • f0bb9a7f39 target/riscv: Generate nanboxed results from trans_rvf.inc.c Richard Henderson 2021-03-08 12:26:47 -0500
  • 52f2d5cbee target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Richard Henderson 2021-03-08 12:24:18 -0500
  • adb4d9907a target/riscv: Generate nanboxed results from fp helpers Richard Henderson 2021-03-08 12:21:50 -0500
  • 1a4d0973f0 target/riscv/vector_helper: Fix build on 32-bit big endian hosts Thomas Huth 2021-03-08 12:18:26 -0500
  • 0f95c05ca4 target/riscv: fix vector index load/store constraints LIU Zhiwei 2021-03-08 12:16:43 -0500
  • fdfa52f424 target/riscv: Quiet Coverity complains about vamo* LIU Zhiwei 2021-03-08 12:15:47 -0500
  • cd956f5aa6 target/riscv: Fix pmp NA4 implementation Alexandre Mergnat 2021-03-08 12:14:42 -0500
  • b1e52b7958 target/riscv: fix vill bit index in vtype register Frank Chang 2021-03-08 12:13:56 -0500
  • 61d69c8175 target/riscv: fix return value of do_opivx_widen() Frank Chang 2021-03-08 12:13:15 -0500
  • 98982dbe49 target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Frank Chang 2021-03-08 12:12:34 -0500
  • d75c8e7fcf target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion Frank Chang 2021-03-08 12:11:00 -0500
  • 798ce750d5 target/arm/cpu: Update coding style to make checkpatch.pl happy Philippe Mathieu-Daudé 2021-03-08 11:35:17 -0500
  • de7bcbae57 target/arm: Use TCF0 and TFSRE0 for unprivileged tag checks Peter Collingbourne 2021-03-08 11:33:54 -0500