10 commits

Author	SHA1	Message	Date
Paolo Bonzini	96e7e32972	softmmu: support up to 12 MMU modes ... At 8k per TLB (for 64-bit host or target), 8 or more modes make the TLBs bigger than 64k, and some RISC TCG backends do not like that. On the affected hosts, cut the TLB size in half---there is still a measurable speedup on PPC with the next patch. Backports commit 1de29aef17a7d70dbc04a7fe51e18942e3ebe313 from qemu	2018-02-13 08:34:52 -05:00
Peter Maydell	933e3bd8d1	Add MemTxAttrs to the IOTLB ... Add a MemTxAttrs field to the IOTLB, and allow target-specific code to set it via a new tlb_set_page_with_attrs() function; pass the attributes through to the device when making IO accesses. Backports commit fadc1cbe85c6b032d5842ec0d19d209f50fcb375 from qemu	2018-02-12 18:38:38 -05:00
Peter Maydell	2aecce835b	Make CPU iotlb a structure rather than a plain hwaddr ... Make the CPU iotlb a structure rather than a plain hwaddr; this will allow us to add transaction attributes to it. Backports commit e469b22ffda40188954fafaf6e3308f58d50f8f8 from qemu	2018-02-12 18:34:05 -05:00
xorstream	69ae8f7987	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
xorstream	72a497bc14	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
xorstream	770c5616e2	Automated leading tab to spaces conversion.	2017-01-21 12:28:22 +11:00
xorstream	fac6a66860	platform.h move #3	2017-01-21 00:13:21 +11:00
xorstream	002151874a	Unicorn interface working with test app in 32bit and 64bit builds.	2017-01-20 17:27:22 +11:00
xorstream	1aeaf5c40d	This code should now build the x86_x64-softmmu part 2.	2017-01-19 22:50:28 +11:00
Nguyen Anh Quynh	344d016104	import	2015-08-21 15:04:50 +08:00