2 commits

Author	SHA1	Message	Date
Alistair Francis	b23e786779	riscv: spike: Remove target macro conditionals ... Backports dc4d4aaee31cd3ac4020d3b15729f0a104ce8862	2021-03-08 15:20:41 -05:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00