5 commits

Author	SHA1	Message	Date
Alistair Francis	2e6d11ee47	target/riscv: Add Hypervisor CSR macros ... Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Backports commit 71f09a5bb48d0c51b87e70158407ec2db4a9c6e2 from qemu	2019-05-28 19:17:54 -04:00
Alistair Francis	c64f57c360	target/riscv: Add the MPV and MTL mstatus bits ... Backports commit 49aaa3e534f5422a56313bb93c1880e70fc1da7e from qemu	2019-05-28 19:15:33 -04:00
Alistair Francis	4b0355dcfc	target/riscv: Mark privilege level 2 as reserved ... Backports commit 356d74192a035c71a78a22d24812a6df6099ae40 from qemu	2019-05-28 19:12:10 -04:00
Jim Wilson	30ab335bb3	RISC-V: Fixes to CSR_* register macros. ... This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu	2019-03-19 23:39:49 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00