53 commits

Author	SHA1	Message	Date
Alex Bennée	ff0ff28939	target-arm: don't generate WFE/YIELD calls for MTTCG ... The WFE and YIELD instructions are really only hints and in TCG's case they were useful to move the scheduling on from one vCPU to the next. In the parallel context (MTTCG) this just causes an unnecessary cpu_exit and contention of the BQL. Backports commit c22edfebff29f63d793032e4fbd42a035bb73e27 from qemu	2018-03-02 10:27:36 -05:00
Peter Maydell	bddeac4430	target/arm: A32, T32: Create Instruction Syndromes for Data Aborts ... Add support for generating the ISS (Instruction Specific Syndrome) for Data Abort exceptions taken from AArch32. These syndromes are used by hypervisors for example to trap and emulate memory accesses. This is the equivalent for AArch32 guests of the work done for AArch64 guests in commit aaa1f954d4cab243. Backports commit 9bb6558a218bf7e466e5ac1100639517d8a30d33 from qemu	2018-03-02 00:37:06 -05:00
Thomas Huth	b2f1326437	Move target-* CPU file into a target/ folder ... We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu	2018-03-01 22:50:58 -05:00

Renamed from qemu/target-arm/translate-a64.c (Browse further)