52 commits

Author	SHA1	Message	Date
Jim Wilson	65903cf9a4	RISC-V: Add debug support for accessing CSRs. ... Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function to set it. Disable mode checks when debugger field true. Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu	2019-03-19 23:42:48 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00