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4 commits

Author SHA1 Message Date
mothran 6b521e9e9b update the sparc reg read/write to include o/l/i registers 2015-09-14 20:03:32 -07:00
Nguyen Anh Quynh 548355acca sparc: do not accept BIGENDIAN mode in samples. more sanity check should be done in the core 2015-09-11 14:02:27 +08:00
Nguyen Anh Quynh 1724fabb05 add shebang for regress/sparc_reg.py 2015-09-08 09:14:22 +08:00
Ryan Hileman 5f6c475479 add regress for #126 2015-09-07 18:08:05 -07:00