3 commits

Author	SHA1	Message	Date
Richard Henderson	47b797f1bb	target/riscv: Use env_cpu, env_archcpu ... Cleanup in the boilerplate that each target must define. Replace riscv_env_get_cpu with env_archcpu. The combination CPU(riscv_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 3109cd98a6c0c618189b38a83a8aa29cb20acbce from qemu	2019-06-12 12:06:19 -04:00
Jonathan Behrens	25c0333213	target/riscv: Do not allow sfence.vma from user mode ... The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Backports commit b86f4167630802128d94f3c89043d97d2f4c2546 from qemu	2019-05-28 18:29:46 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00