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69 commits

Author SHA1 Message Date
Paolo Bonzini fa2b872b0b
target-i386: avoid overflow in the tsc-frequency property
The TSC frequency fits comfortably in an int when expressed in kHz,
but it may overflow when converted to Hz. In this case,
tsc-frequency returns a negative value because x86_cpuid_get_tsc_freq
does a 32-bit multiplication before assigning to int64_t.

For simplicity just make tsc_khz a 64-bit value.

Backports commit 06ef227e5158cca6710e6c268d6a7f65a5e2811b from qemu
2018-02-17 15:23:17 -05:00
Paolo Bonzini 6153671333
target-i386: add support for SMBASE MSR and SMIs
Apart from the MSR, the smi field of struct kvm_vcpu_events has to be
translated into the corresponding CPUX86State fields. Also,
memory transaction flags depend on SMM state, so pull it from struct
kvm_run on every exit from KVM to userspace.

Backports relevant parts of commit fc12d72e10828ca6ff75f2ad432b741f07a10cef from qemu
2018-02-17 15:23:16 -05:00
Paolo Bonzini 1fed54da89
target-i386: mask NMIs on entry to SMM
QEMU is not blocking NMIs on entry to SMM. Implementing this has to
cover a few corner cases, because:

- NMIs can then be enabled by an IRET instruction and there
is no mechanism to _set_ the "NMIs masked" flag on exit from SMM:
"A special case can occur if an SMI handler nests inside an NMI handler
and then another NMI occurs. [...] When the processor enters SMM while
executing an NMI handler, the processor saves the SMRAM state save map
but does not save the attribute to keep NMI interrupts disabled.

- However, there is some hidden state, because "If NMIs were blocked
before the SMI occurred [and no IRET is executed while in SMM], they
are blocked after execution of RSM." This is represented by the new
HF2_SMM_INSIDE_NMI_MASK bit. If it is zero, NMIs are _unblocked_
on exit from RSM.

Backports commit 9982f74bad70479939491b69522da047a3be5a0d from qemu
2018-02-13 12:29:31 -05:00
Lioncash 25a58231fc
target-i386: Use correct memory attributes for memory accesses
These include page table walks, SVM accesses and SMM state save accesses.

The bulk of the patch is obtained with

sed -i 's/\(\<[a-z_]*_phys\(_notdirty\)\?\>(cs\)->as,/x86_\1,/'

Backports commit b216aa6c0fcbaa8ff4128969c14594896a5485a4 from qemu
2018-02-13 11:54:12 -05:00
Paolo Bonzini dc80b0893f
target-i386: introduce cpu_get_mem_attrs
Backports commit f794aa4a2fd772a3ec413c4e478cc23857cfee98 from qemu
2018-02-13 11:33:39 -05:00
Eduardo Habkost 79df79434d
target-i386: Fix signedness of MSR_IA32_APICBASE_BASE
Existing definition triggers the following when using clang
-fsanitize=undefined:

hw/intc/apic_common.c:314:55: runtime error: left shift of 1048575 by 12
places cannot be represented in type 'int'

Fix it so we won't try to shift a 1 to the sign bit of a signed integer.

Backports commit 458cf469f4a1cb520b07092f5537c5a6d2389d23 from qemu
2018-02-13 08:17:18 -05:00
Emilio G. Cota df41e9ffd3
target-i386: remove superfluous TARGET_HAS_SMC macro
Backports commit 9c04146ad4696b20c440bfbb4a6ab27ea254e7ca from qemu
2018-02-12 16:41:55 -05:00
Eduardo Habkost 81cae9834a
target-i386: Move CPUX86State.cpuid_apic_id to X86CPU.apic_id
The field doesn't need to be inside CPUState, and it is not specific for
the CPUID instruction, so move and rename it.

Backports commit 9e9d3863adcbd1ffeca30f240f49805b00ba0d87 from qemu
2018-02-12 15:44:11 -05:00
Eduardo Habkost 51b49a5b97
target-i386: Eliminate cpu_init() function
Instead of putting extra logic inside cpu.h, just do everything inside
cpu_x86_init_user().

Backports commit 15258d46baef5f8265ad5f1002905664cf58f051 from qem
2018-02-12 15:35:44 -05:00
Eduardo Habkost 68fa057b7c
target-i386: Rename cpu_x86_init() to cpu_x86_init_user()
The function is used only for CONFIG_USER, so make its purpose clear.

Backports commit 644dba250a3ed04079792f0d6cc918fb1483e6a5 from qemu
2018-02-12 15:31:29 -05:00
Paolo Bonzini 5b02b2728a
target-i386: make xmm_regs 512-bit wide
Right now, the AVX512 registers are split in many different fields:
xmm_regs for the low 128 bits of the first 16 registers, ymmh_regs
for the next 128 bits of the same first 16 registers, zmmh_regs
for the next 256 bits of the same first 16 registers, and finally
hi16_zmm_regs for the full 512 bits of the second 16 bit registers.

This makes it simple to move data in and out of the xsave region,
but would be a nightmare for a hypothetical TCG implementation and
leads to a proliferation of [XYZ]MM_[BWLSQD] macros. Instead,
this patch marshals data manually from the xsave region to a single
32x512-bit array, simplifying the macro jungle and clarifying which
bits are in which vmstate subsection.

The migration format is unaffected.

Backports commit b7711471f551aa4419f9d46a11121f48ced422da from qemu
2018-02-12 12:38:43 -05:00
Richard Henderson 77b03e0973
target-i386: Make check_hw_breakpoints static
The function is now only used from within a single file.

Backports commit dd941cdcfec536aad6a310a153778142ed9f3e92 from qemu
2018-02-11 12:28:08 -05:00
xorstream 72a497bc14 Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
xorstream 770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream 002151874a Unicorn interface working with test app in 32bit and 64bit builds. 2017-01-20 17:27:22 +11:00
xorstream 1aeaf5c40d This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
Andrew Dutcher 3a1f231e8f eflags patch 2016-08-09 19:38:44 -07:00
Nguyen Anh Quynh 51323c9c17 x86: properly calculate EFLAGS when UC_HOOK_CODE is used. this should fix issue #246 2015-11-05 20:26:39 +08:00
Nguyen Anh Quynh 344d016104 import 2015-08-21 15:04:50 +08:00