Commit graph

219 commits

Author SHA1 Message Date
Peter Maydell db8b0a82b1
cpu: Support a target CPU having a variable page size
Support target CPUs having a page size which isn't knownn
at compile time. To use this, the CPU implementation should:
* define TARGET_PAGE_BITS_VARY
* not define TARGET_PAGE_BITS
* define TARGET_PAGE_BITS_MIN to the smallest value it
might possibly want for TARGET_PAGE_BITS
* call set_preferred_target_page_bits() in its realize
function to indicate the actual preferred target page
size for the CPU (and report any error from it)

In CONFIG_USER_ONLY, the CPU implementation should continue
to define TARGET_PAGE_BITS appropriately for the guest
OS page size.

Machines which want to take advantage of having the page
size something larger than TARGET_PAGE_BITS_MIN must
set the MachineClass minimum_page_bits field to a value
which they guarantee will be no greater than the preferred
page size for any CPU they create.

Note that changing the target page size by setting
minimum_page_bits is a migration compatibility break
for that machine.

For debugging purposes, attempts to use TARGET_PAGE_SIZE
before it has been finally confirmed will assert.

Backports commit 20bccb82ff3ea09bcb7c4ee226d3160cab15f7da from qemu
2018-02-26 12:29:08 -05:00
Vijaya Kumar K a7229cc08a
translate-all.c: Compute L1 page table properties at runtime
Remove L1 page mapping table properties computing
statically using macros which is dependent on
TARGET_PAGE_BITS. Drop macros V_L1_SIZE, V_L1_SHIFT,
V_L1_BITS macros and replace with variables which are
computed at early stage of VM boot.

Removing dependency can help to make TARGET_PAGE_BITS
dynamic.

Backports commit 66ec9f49399f0a9fa13ee77c472caba0de2773fc from qemu
2018-02-26 11:46:58 -05:00
Peter Lieven 799bf1c3a5
exec: avoid realloc in phys_map_node_reserve
this is the first step in reducing the brk heap fragmentation
created by the map->nodes memory allocation. Since the introduction
of RCU the freeing of the PhysPageMaps is delayed so that sometimes
several hundred are allocated at the same time.

Even worse the memory for map->nodes is allocated and shortly
afterwards reallocated. Since the number of nodes it grows
to in the end is the same for all PhysPageMaps remember this value
and at least avoid the reallocation.

The large number of simultaneous allocations (about 450 x 70kB in
my configuration) has to be addressed later.

Backports commit 101420b886eec36990419bc9ed5b503622af8a0d from qemu
2018-02-25 19:32:40 -05:00
Lioncash c658126845
include: Move RAMList to ramlist.h
Moves the struct back into qemu's headers
2018-02-20 08:47:51 -05:00
Lioncash cdd4003ce9
Move RAMBlock to ram_addr.h
Moves it back into qemu's includes.
2018-02-20 08:35:44 -05:00
Lioncash b2a8355f8d
target-i386: Correct unicorn macro 2018-02-19 01:00:47 -05:00
Mike Day 2b93290eea
exec: convert ram_list to QLIST
QLIST has RCU-friendly primitives, so switch to it.

Backports commit 0d53d9fe8a0dcb849bc7c9836e9e6a287f9aa787 from qemu
2018-02-18 18:49:24 -05:00
Dr. David Alan Gilbert cc088f84b5
qemu_ram_block_from_host
Postcopy sends RAMBlock names and offsets over the wire (since it can't
rely on the order of ramaddr being the same), and it starts out with
HVA fault addresses from the kernel.

qemu_ram_block_from_host translates a HVA into a RAMBlock, an offset
in the RAMBlock and the global ram_addr_t value.

Rewrite qemu_ram_addr_from_host to use qemu_ram_block_from_host.

Provide qemu_ram_get_idstr since its the actual name text sent on the
wire.

Backports commit 422148d3e56c3c9a07c0cf36c1e0a0b76f09c357 from qemu
2018-02-17 17:54:03 -05:00
Peter Maydell e1a4e4208f
pc: resizeable ROM blocks
This makes ROM blocks resizeable. This infrastructure is required for other
functionality we have queued.

Backports commit aaf03019175949eda5087329448b8a0033b89479 from qemu
2018-02-17 17:18:38 -05:00
Paolo Bonzini 96e5a7ced3
tcg: introduce tcg_current_cpu
This is already useful on Windows in order to remove tls.h, because
accesses to current_cpu are done from a different thread on that
platform. It will be used on POSIX platforms as soon TCG stops using
signals to interrupt the execution of translated code.

Backports commit 9373e63297c43752f9cf085feb7f5aed57d959f8 from qemu
2018-02-17 15:23:49 -05:00
Paolo Bonzini 5c85c564b5
exec: Atomic access to bounce buffer
There could be a race condition when two processes call
address_space_map concurrently and both want to use the bounce buffer.

Add an in_use flag in BounceBuffer to sync it.

Backports commit c2cba0ffe495b60c4cc58080281e99c7a6580d4b from qemu
2018-02-12 21:00:17 -05:00
MerryMage 4128f3b259 aarch64: Add FPCR and FPSR registers 2018-01-16 17:37:47 +00:00
MerryMage f90c819a33 aarch64: Add pstate pseudoregister 2018-01-16 17:37:17 +00:00
bunnei 73f4573535 aarch64: Add exception syndrome pseudo register. 2018-01-03 19:41:12 -05:00
Tasuku SUENAGA a.k.a. gunyarakun da5f2fc883 Fix wrong register aliases on arm64 (#922) 2017-12-20 22:09:38 +08:00
Nguyen Anh Quynh e6c27cfbd5 LGPL2 for all header files under include/unicorn/ 2017-12-16 10:08:42 +08:00
Nguyen Anh Quynh fe466d003a callback to count number of instructions in uc_emu_start() should be executed first. fix #727 2017-06-16 13:22:38 +08:00
misson20000 3fdb2d2442 add architecture query (#842) 2017-05-21 09:47:02 +08:00
bulaza 14222bd5f0 Update UC_HOOK_MEM_VALID (#837)
* Update UC_HOOK_MEM_VALID

UC_HOOK_MEM_READ fires before handlers for invalid memory reads, so UC_HOOK_MEM_VALID would technically also be receiving invalid memory reads. Switching to UC_HOOK_MEM_READ_AFTER ensures that only actually valid reads are hooked

* Removed macro change, added comment

Removed the macro change, but added a clarifying comment. May submit a future PR with a new macro added

* Update unicorn.h

will -> may

* Update unicorn.h
2017-05-18 08:12:46 +07:00
misson20000 014ccfb94a Aarch64 add thread registers (#834)
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 14:42:49 +07:00
bulaza 476553223b Fixing issues with const_generator.py (#832) 2017-05-14 00:16:48 +07:00
bulaza 4b9efdc986 Adding INSN hook checks for x86 (#833)
* adding INSN hook checking for x86

* tabs to spaces

* need to return bool not uc_err

* fixed conditional after switching to bool
2017-05-14 00:16:17 +07:00
bulaza e95edd37f3 Update unicorn.h (#821)
Further clarifying the comments I PRed last week.
2017-05-06 22:32:00 +08:00
Ryan Hileman 187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
bulaza c09a52e803 Update comments on UC_MEM_*_UNMAPPED (#811)
Updated the comment on UC_MEM_*_UNMAPPED to clarify what happens if "true" is returned
2017-04-27 09:29:01 +08:00
bulaza f6908f03a9 Updated uc_close comment to clarify usage (#805) 2017-04-24 23:55:18 +08:00
Nguyen Anh Quynh dd07ae607c bump extra version to 2 2017-04-21 15:30:40 +08:00
Nguyen Anh Quynh e917c9de10 Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
Nguyen Anh Quynh 5dbc640b9a bump UC_VERSION_EXTRA to 1 2017-04-20 14:14:24 +08:00
Nguyen Anh Quynh 3b6779479e cleanup uc_priv.h 2017-03-30 15:59:13 +08:00
Nguyen Anh Quynh 094ca80092 fix conflicts 2017-03-30 12:23:24 +08:00
zhangwm d8fe34a2e8 armeb: Add support for ARM big endian. 2017-03-13 22:32:44 +08:00
Nguyen Anh Quynh c01dcf0a14 fix merge conflicts 2017-03-10 21:04:33 +08:00
Nguyen Anh Quynh f4325f8c4e bindings: update to support X86 MSR id 2017-02-24 21:51:01 +08:00
Ahmed Samy 02e6c14e12 x86: add MSR API via reg API (#755)
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...

So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
	Byte	Value		Size
	0	MSR ID		4
	4       MSR val		8
2017-02-24 21:37:19 +08:00
Nguyen Anh Quynh 6ea39f7d5a merge msvc with master 2017-02-24 10:39:36 +08:00
fG! d5870ff47d Update unicorn.h (#753)
Make it clear that only very few instructions can be hooked
2017-02-21 10:22:17 +08:00
vardyh 7f9251511e MSVC port (vardyh) (#746)
* unicorn: use waitable timer to implement usleep() on Windows

Signed-off-by: vardyh <vardyh.dev@gmail.com>

* atomic: implement barrier() for msvc

Signed-off-by: vardyh <vardyh.dev@gmail.com>
2017-02-07 21:31:35 +08:00
Nguyen Anh Quynh b616115df1 update ChangeLog 2017-01-25 12:00:18 +08:00
Parker Thompson 053ecd7bf4 Added ARM coproc registers (#684)
* Added ARM coproc registers

* Added regression test for vfp
2017-01-25 11:56:19 +08:00
xorstream 2a941e3efb Finalise MSVC port (#739)
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file

* Arm issue fix.

* Finalise MSVC port.
2017-01-24 22:09:33 +08:00
xorstream 8e45102b43 Arm support ported. (#736)
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file
2017-01-23 23:30:57 +08:00
Nguyen Anh Quynh a0f7b526bd cleanup include/unicorn/*.h 2017-01-22 06:02:07 +08:00
xorstream 9fac29d154 Changed some MSVC compatibility defines based on MSVC version. (#724) 2017-01-21 20:21:27 +08:00
Nguyen Anh Quynh e98a396e68 fix include path of platform.h 2017-01-21 11:31:29 +08:00
Nguyen Anh Quynh 330e7cb87b cleanup platform.h 2017-01-21 11:02:59 +08:00
xorstream 770c5616e2 Automated leading tab to spaces conversion. 2017-01-21 12:28:22 +11:00
xorstream 429bfca48e Fixes for MSVC native support to still work with GCC/GNU. 2017-01-21 01:07:10 +11:00
xorstream fac6a66860 platform.h move #3 2017-01-21 00:13:21 +11:00
xorstream f4b375c651 platform.h moved. 2017-01-21 00:03:50 +11:00