3 commits

Author	SHA1	Message	Date
LIU Zhiwei	7d0d7338c2	target/riscv: add vector amo operations ... Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d	2021-02-26 09:47:32 -05:00
LIU Zhiwei	c7a17d04a2	target/riscv: add vector stride load and store instructions ... Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7	2021-02-26 02:55:14 -05:00
LIU Zhiwei	e4bc5056cd	target/riscv: add an internals.h header ... The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Backports f476f17740ad42288d42dd8fedcdae8ca7007a16	2021-02-26 02:39:29 -05:00