unicorn

yuzu/unicorn

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Author	SHA1	Message	Date
Jim Wilson	30ab335bb3	RISC-V: Fixes to CSR_* register macros. This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu	2019-03-19 23:39:49 -04:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00

Author

SHA1

Message

Date

Jim Wilson

30ab335bb3

RISC-V: Fixes to CSR_* register macros.

This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Backports commit 8e73df6aa3f2f0e5c26c03a94a88406616291815 from qemu

2019-03-19 23:39:49 -04:00

Lioncash

b6f752970b

target/riscv: Initial introduction of the RISC-V target

This ports over the RISC-V architecture from Qemu. This is currently a
very barebones transition. No code hooking or any fancy stuff.
Currently, you can feed it instructions and query the CPU state itself.

This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit
is desirable through Unicorn's interface as well.

Extremely basic examples of executing a single instruction have been
added to the samples directory to help demonstrate how to use the basic
functionality.

2019-03-08 21:46:10 -05:00

2 commits