2 commits

Author	SHA1	Message	Date
LIU Zhiwei	c7a17d04a2	target/riscv: add vector stride load and store instructions ... Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7	2021-02-26 02:55:14 -05:00
LIU Zhiwei	9db3b70869	target/riscv: add vector configure instruction ... vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu	2021-02-26 02:37:59 -05:00