5 commits

Author	SHA1	Message	Date
Richard Henderson	ce54dfb4f7	target/riscv: Check nanboxed inputs to fp helpers ... If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. Backports 00e925c56074f8c4923a087e2eecea8a3315ea40	2021-03-08 12:31:18 -05:00
Richard Henderson	adb4d9907a	target/riscv: Generate nanboxed results from fp helpers ... Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Backports 9921e3d3306c344aceeabe074d5bcaafcc6acafb	2021-03-08 12:21:58 -05:00
LIU Zhiwei	f9c9716534	target/riscv: vector floating-point classify instructions ... Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c	2021-03-07 11:55:45 -05:00
Alex Bennée	14b401f0bf	target/riscv: rationalise softfloat includes ... We should avoid including the whole of softfloat headers in cpu.h and explicitly include it only where we will be calling softfloat functions. We can use the -types.h and -helpers.h in cpu.h for the few bits that are global. Backports commit 135b03cb9defbd080b8834b30e3d45bed00c6137 from qemu	2019-11-18 21:17:03 -05:00
Lioncash	b6f752970b	target/riscv: Initial introduction of the RISC-V target ... This ports over the RISC-V architecture from Qemu. This is currently a very barebones transition. No code hooking or any fancy stuff. Currently, you can feed it instructions and query the CPU state itself. This also allows choosing whether or not RISC-V 32-bit or RISC-V 64-bit is desirable through Unicorn's interface as well. Extremely basic examples of executing a single instruction have been added to the samples directory to help demonstrate how to use the basic functionality.	2019-03-08 21:46:10 -05:00