7 commits

Author	SHA1	Message	Date
Richard Henderson	ce54dfb4f7	target/riscv: Check nanboxed inputs to fp helpers ... If a 32-bit input is not properly nanboxed, then the input is replaced with the default qnan. Backports 00e925c56074f8c4923a087e2eecea8a3315ea40	2021-03-08 12:31:18 -05:00
Richard Henderson	adb4d9907a	target/riscv: Generate nanboxed results from fp helpers ... Make sure that all results from single-precision scalar helpers are properly nan-boxed to 64-bits. Backports 9921e3d3306c344aceeabe074d5bcaafcc6acafb	2021-03-08 12:21:58 -05:00
LIU Zhiwei	b75de9504c	target/riscv: integer scalar move instruction ... Backports 9fc08be626a96ae1ac0cffb22f30ae652c1c645a	2021-03-07 12:38:41 -05:00
LIU Zhiwei	f9c9716534	target/riscv: vector floating-point classify instructions ... Backports 121ddbb36f17d24a7f39d6024d9b3145d154a98c	2021-03-07 11:55:45 -05:00
LIU Zhiwei	7d0d7338c2	target/riscv: add vector amo operations ... Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Backports 268fcca66bde62257960ec8d859de374315a5e3d	2021-02-26 09:47:32 -05:00
LIU Zhiwei	c7a17d04a2	target/riscv: add vector stride load and store instructions ... Vector strided operations access the first memory element at the base address, and then access subsequent elements at address increments given by the byte offset contained in the x register specified by rs2. Vector unit-stride operations access elements stored contiguously in memory starting from the base effective address. It can been seen as a special case of strided operations. Backports 751538d5da557e5c10e5045c2d27639580ea54a7	2021-02-26 02:55:14 -05:00
LIU Zhiwei	e4bc5056cd	target/riscv: add an internals.h header ... The internals.h keeps things that are not relevant to the actual architecture, only to the implementation, separate. Backports f476f17740ad42288d42dd8fedcdae8ca7007a16	2021-02-26 02:39:29 -05:00