Richard Henderson 03e2d64aed target/arm: Convert jazelle from feature bit to isar1 test ... Having V6 alone imply jazelle was wrong for cortex-m0. Change to an assertion for V6 & !M. This was harmless, because the only place we tested ARM_FEATURE_JAZELLE was for 'bxj' in disas_arm(), which is unreachable for M-profile cores. Backports commit 09cbd50198d5dcac8bea2e47fa5dd641ec505fae from qemu		2018-11-10 08:24:11 -05:00
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arm	target/arm: Convert jazelle from feature bit to isar1 test	2018-11-10 08:24:11 -05:00
i386	target/i386: Convert to HAVE_CMPXCHG128	2018-10-23 15:21:03 -04:00
m68k	Removes accessible assert	2018-10-06 05:02:20 -04:00
mips	target/mips: Add opcodes for nanoMIPS EVA instructions	2018-10-23 14:33:08 -04:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00