LIU Zhiwei 0554e79ad1 target/riscv: support vector extension csr ... The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Backports 8e3a1f18871e0ea251b95561fe1ec5a9bc896c4a from qemu		2021-02-26 02:25:58 -05:00
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arm	target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64	2021-02-25 23:50:18 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: support vector extension csr	2021-02-26 02:25:58 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00