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Peter Maydell 05add081a3
target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL 
The M-profile CONTROL register has two bits -- SFPA and FPCA --
which relate to floating-point support, and should be RES0 otherwise.
Handle them correctly in the MSR/MRS register access code.
Neither is banked between security states, so they are stored
in v7m.control[M_REG_S] regardless of current security state.

Backports commit 2e1c5bcd32014c9ede1b604ae6c2c653de17fc53 from qemu
2019-04-30 10:21:24 -04:00
..
arm target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL 2019-04-30 10:21:24 -04:00
i386 tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
m68k tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
mips tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
riscv tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00
sparc tcg: Hoist max_insns computation to tb_gen_code 2019-04-30 09:49:57 -04:00